counters / an001

agfa

re: nco/pwm sample code the line
crta := %00100_000 << 23 + 1 << 9·+ 0
sets bit9, the bpin lsb, if i understand.· why is that?

also is there more counter documentation?

edit:
i see no difference on the output if i remove "+ 1 << 9 +0" from the line

Post Edited (agfa) : 8/10/2008 2:46:02 PM GMT

Phil Pilgrim (PhiPi)

That example contains a little bit of misdirection. However, if you note the comment on the same line, it says, "BPIN is ignored". What this means is that the 1 << 9 has no effect. However, if the line had read,

ctra := %00101_000 << 23 + 1 << 9 + 0

then the 1 << 9 would indicate a complementary output on BPIN which, in this case, would be pin 1.

So the reason deleting + 1 << 9 + 0 didn't change anything is twofold:

1) the 1 << 9 was ignored to begin with, and
2) deleting 0 doesn't change the value of the expression. APIN is still 0.

The example contains yet further misdirection in the _000 part of %00100_000. In the PLL modes, these three bits indicate the value of the clock division. In NCO modes, they have no effect whatsoever and can take any value. My preference would be to express it %00100 << 26 instead, which removes any implied significance from the "PLL" bits.

-Phil

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Post Edited (Phil Pilgrim (PhiPi)) : 8/10/2008 4:42:52 PM GMT

agfa

so the value of xpin·determines the i/o pin?

edit:
ok, i tried it, thats what it appears to do.· i was unable to get that from the note.

thanks phil

Post Edited (agfa) : 8/10/2008 7:42:09 PM GMT

agfa

now a question about pll single ended mode.

according to the table 2 on pg 3, the output is PLLx.· figure 5 on page 9 indicates input as "clock in".· is the input the system clock, or pin 31 of PHSA, or what?· how does the FRQA come in to play?

by playing around with it i see that FRQA does effect it, but i can't predict what it's doing.

edit:· on a second look i see that there is a phase compare in the figure.· i would still like some insight.

Post Edited (agfa) : 8/11/2008 12:27:52 PM GMT

Phil Pilgrim (PhiPi)

PLL mode is like NCO mode, except that a 16x PLL clock muliplier stage, plus a tapped digital divider stage follows the counter. The input to the PLL clock multiplier is PHSx[noparse][[/noparse]31]. The divider tap is chosen by bits 25 .. 23 of CTRx. The value of FRQx determines the frequency feeding the PLL and is calculated the same as for NCO mode. However, this time it must be between 4MHz and 8MHz to ensure PLL stability.

-Phil

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agfa

thats how i expected it to work, but i overclocked it.· must have read the 4 to 8 Mhz limitation a half dozen times, just didn't gell till i read your response.

thanks again.