watchdog wakeup issue

Peter Verkaik

Here is some sx48 assembly code that is part of the javelin firmware.
It is the startup code and the nap() function implementation.
The trouble is that using nap(), the javelin goes to sleep but appears to never wakeup.
As far as I can tell the code looks solid to me, assuming the
call stack is preserved during sleep.

This code was sent to me by Chris Waters who wrote the javelin firmware.
Anybody notice something why this code should not wakeup the sx48?

Regards peter


Here is the relevant code. DoInit is the reset vector.
I am interested if you see any issues here. Nap definitely used to work
since I remember testing it with Andy Lindsay years ago.

; ==============================================================================
;· Nap(Prescale)
; ==============================================================================
;· Description:
;····· Sleep for a period of time based on the prescaler.
;· Parameters:
;····· Prescale = %000 - %111
; ==============================================================================
nmPrescale······· =············ nmBlockTimeoutL··············· ;1st Parameter = Timeout

nm_jstamp_core_CPU_nap
··············· bank····· nmBlockBank························· ;Change to blocking bank (FSR pointing to port select)
··············· mov······ w,nmPrescale
··············· and······· w,#%00000111······················· ;Mask out the high bits.
··············· or··········· w,#%10011000···················· ;Update the timeout.
··············· mov······ !option,w
··············· call········· @nmSleep························ ;Perform the sleep.
··············· jmp······· @nmReturnNone······················ ;Yes => Complete

··············· org········ $C00
nmSleep
··············· ; Save the IO directions.
··············· mov······ w, #$0F····························· ;1··········· Prepare to read DDR
··············· mov······ m, w································ ;1··········· Prepare to read DDR
··············· mov······ !nmPort0, w························· ;1··········· w = DDR
··············· mov······ OP_LSB, w
··············· mov······ !nmPort1, w························· ;1··········· w = DDR
··············· mov······ OP_MSB, w··························· ;1··········· Store DDR in temp variable
··············· sleep
··············· ; Never returns, return is done on startup.

; Initialise the processor
_ProcInit
··············· mov······ !option,#%10011111·················· ; Enable RTCC rollover.
_IOInit
··············· _bank·· Debugger
··············· clr·········· tx_Count
··············· bank····· JVMVars
··············· mov······ w,#$1D
··············· mov······ m,w
··············· mov······ !rb,#%00000000······················ ; Enable CMOS levels on all inputs.
··············· mov······ !rc,#%00000000
··············· mov······ m,#MODE_WRITE_DIR
··············· mov······ ra, #%00001111······················ ;CS and WE = high, Dout = high
··············· mov······ !ra, #%00000010····················· ;ra is all outputs except Din
··············· mov······ !rb, #%11111111····················· ;rb is Port0 and defaults to all inputs
··············· mov······ !rc, #%11111111····················· ;rc is Port1 and defaults to all inputs
··············· mov······ !rd, #%00000000····················· ;rd is all outputs (undefined value)
··············· mov······ !re, #%11111111····················· ;re is SRAM Data and defaults to all inputs
··············· retp

;

---

; Subroutine: Wake
;
; Wake up after a nap or sleep operation.
;

---

Wake··· ; Restore the DDR.
··············· mov······ w, OP_LSB
··············· mov······ !nmPort0, w·························· ;1··········· w = DDR
··············· mov······ w, OP_MSB
··············· mov······ !nmPort1, w·························· ;1··········· w = DDR
··············· mov······ !option,#%10011111··················· ; Renable RTCC rollover.
··············· retp··········································· ; Return from the nmSleep routine.

;**************************************************************************
; Initialisation
;
;·············· This is the actual reset vector. It will be reached on power on
;·············· and watchdog reset.
;**************************************************************************
DoInit··· ; Check for watchdog reset.
··············· call········· @IOInit
··············· jb··········· to,[noparse]:p[/noparse]or
··············· jnb········ pd,Wake···························· ; Sleep wakeup
··············· ; Start power on reset.
[noparse]:p[/noparse]or········call········· @RAMInit····························· ; Initialise RAM
··············· call········· @nmIsrCreate
··············· call········· @ProcInit························ ; Initialise the processor
; Send a byte to indicate that we are starting the reload.
··············· mov······ w,#comStartLoad
··············· call········· @DebugSendReply

Regards,
Chris.

william chan

What happened to Chris Walters?

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
www.fd.com.my
www.mercedes.com.my

Peter Verkaik

He moved on to do other things and is no longer maintaining the javelin IDE.
At present I maintain the IDE.

regards peter