Intel following multicore model
Oldbitcollector (Jeff)
Posts: 8,091
I love how Parallax is so ahead of the curve...
"Intel says to prepare for 'thousands of cores'"
news.cnet.com/8301-13924_3-9981760-64.html?part=rss&subj=news&tag=2547-1_3-0-5
Any chance Chip *might* own the patent on the multi-core idea itself?
<smirk>
OBC
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New to the Propeller?
Getting started with the Protoboard? - Propeller Cookbook 1.4
Updates to the Cookbook are now posted to: Propeller.warrantyvoid.us
Got an SD card? - PropDOS
Need a part? Got spare electronics? - The Electronics Exchange
"Intel says to prepare for 'thousands of cores'"
news.cnet.com/8301-13924_3-9981760-64.html?part=rss&subj=news&tag=2547-1_3-0-5
Any chance Chip *might* own the patent on the multi-core idea itself?
<smirk>
OBC
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
New to the Propeller?
Getting started with the Protoboard? - Propeller Cookbook 1.4
Updates to the Cookbook are now posted to: Propeller.warrantyvoid.us
Got an SD card? - PropDOS
Need a part? Got spare electronics? - The Electronics Exchange
Comments
As far patents go, my guess IBM, TI and Sun would hold some of the early patents on multicores.
As far as number of cores go, Rapport and IBM seems to have beat Intel to the punch on number of cores with the upcoming Kilocore.
FWIW
So, you add cores instead. The problem is that adding cores doesn't always make your application go faster. In fact, we've seen cases on high performance compute applications where a multicore processor was actually *slower* than a single core running at the same clock rate. The reason is that at least one level of the cache is shared between cores. By having twice as many cores, you end up oversubscribing the cache causing more round trips to memory. This is compounded by fact that memory technology isn't keeping pace with processor technology. Back In The Day(tm) memory was as close as 1 clock cycle from the processor. Now, even 1st level cache isn't that close and memory is well over 100 clocks away.
Further, it's not clear how many applications will truely be able to take advantage of the kind of parallelism coming down the pipe from Intel and AMD (who will presumably do something similar). You can already see this in troubles porting some applications to the IBM Cell processors.
Now, the Propeller solves this problem. Unfortunately, its solution isn't ideal either. The Prop's solution is to strictly partition bandwidth between the 8 cores. That is great for predictability because the traffic generated from one core doesn't affect another. However, it's horrible for utilization unless all 8 cores are doing hub operations. If only one core needs access to the hub, you will utilize only 1/8th of the total available bandwidth.
To echo what waltc has said, the Prop, as far ahead as it seems to be in the microcontroller world, isn't the first multicore processor. In fact, the Thinking Machines CM-1 was a multicore chip and that dates back to, I believe, the mid 1980's. There may be examples further back than that, though I wasn't able to find any.
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It is 18 bit instead of 32.
The stacks could be deeper
The direction registers are switched around on a quite a few of the cores. North should mean north, always. Maybe I will understand why they did this when I start programming it.
There are only 64words of RAM & 64words of ROM per core
But most of all, they don't have the great people at their forum like we have here. You guys are amazing, talented, sharing people!
Tanks,
Doug
Leon
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Amateur radio callsign: G1HSM
Suzuki SV1000S motorcycle
Post Edited (Leon) : 7/3/2008 3:08:37 PM GMT
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Paul Baker
Propeller Applications Engineer
Parallax, Inc.