Counter application question
Hi all.
I want to generate a clock of 24Mhz with the pchip.
Using counter in NCO mode, that signal at output will have jitter, cause the value of FRQA <> 2**N.
So, how much jitter ? Could be the signal generated usefull for clocking another processor/FPGA ?
Or, should I use another method for this ?
I need a relative stable 24Mhz, clock, 48Mhz clock, and maybe a 25Mhz clock too.
Just only for some tests... in my FPGA board.
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Regards.
Alberto.
I want to generate a clock of 24Mhz with the pchip.
Using counter in NCO mode, that signal at output will have jitter, cause the value of FRQA <> 2**N.
So, how much jitter ? Could be the signal generated usefull for clocking another processor/FPGA ?
Or, should I use another method for this ?
I need a relative stable 24Mhz, clock, 48Mhz clock, and maybe a 25Mhz clock too.
Just only for some tests... in my FPGA board.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Regards.
Alberto.
Comments
Leon
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Amateur radio callsign: G1HSM
Suzuki SV1000S motorcycle
But my FPGA has only one, and I'm using it.
And I'm needing about two external clks more.
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Regards.
Alberto.
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Paul Baker
Propeller Applications Engineer
Parallax, Inc.
If you put a number like 5000 in PHSA and put the counter in NCO mode and then have the cog monitor the MSB of FRQA and reset FRQA to 0 (or some number) when a toggle is detected, I think you can make more stable frequencies...
Paul idea is easy, just put my frqa := $4000_0000 for 24Mhz and/or frqa := $8000_0000 for 48Mhz with 6MHz xtal.
@Ray. Your idea sounds very good too !! Just only a little bit of programming.
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Regards.
Alberto.