They're not fast enough for use as video ram. For that you need a fast parallel ram which uses a lot of I/O pins. They also don't publicize enough that read cycles are destructive. Every time you read a location, the chip has to write it back. That's not too much of a problem because the write process is very fast, but it does count against the number of write cycles the device can handle before it wears out. If you're using it for a high speed refresh process, that's a lot of read cycles.
Mike Green said...
They're not fast enough for use as video ram. For that you need a fast parallel ram which uses a lot of I/O pins. They also don't publicize enough that read cycles are destructive. Every time you read a location, the chip has to write it back. That's not too much of a problem because the write process is very fast, but it does count against the number of write cycles the device can handle before it wears out. If you're using it for a high speed refresh process, that's a lot of read cycles.
Where did you see that the number of write cycles is limited? I have always thought that they had a virtually unlimited number of write cycles, it's one of their selling points.
Leon
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The FRAM chips do have a very high number of write cycles, much higher than EEPROMs, but you do need to think about endurance when you're doing high speed repetitive operations on the memory.
Have a look at MRAM for the do it all option. Although, it's still got a ways to go to get the density right up there but the prediction is it will compete with Flash/DRAM and eventually replace both them and SRAM.
Which means it could replace CMOS entirely. And have your Prop made from it. [noparse]:)[/noparse]
evanh said...
Which means it could replace CMOS entirely.
Or maybe not. MRAM is not really a logic relevant construction. Also, it seems they are using CMOS fabs to make the stuff anyway. The two techs integrate nicely I presume.
I note they use 10^16 for SRAM/DRAM endurance figures. This is clearly a number that is overly conservative. And I think that'll apply just as much to the 10^15 figure used for MRAM. I guess that's as far as lab testing has gone for each.
As far as I understand MRAM has unlimited endurance just like SRAM/DRAM have.
Marcel P.
Posts: 2
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Leon
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http://pdfserv.maxim-ic.com/en/ds/DS1270AB-DS1270Y.pdf
Leslie
HAM Radio callsign: HA4WV
Where did you see that the number of write cycles is limited? I have always thought that they had a virtually unlimited number of write cycles, it's one of their selling points.
Leon
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Amateur radio callsign: G1HSM
Suzuki SV1000S motorcycle
The FRAM chips do have a very high number of write cycles, much higher than EEPROMs, but you do need to think about endurance when you're doing high speed repetitive operations on the memory.
Leon
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Post Edited (Leon) : 6/23/2008 5:28:53 PM GMT
Which means it could replace CMOS entirely. And have your Prop made from it. [noparse]:)[/noparse]
Here's a prediction of 2015 I guess.
Evan
Evan
I note they use 10^16 for SRAM/DRAM endurance figures. This is clearly a number that is overly conservative. And I think that'll apply just as much to the 10^15 figure used for MRAM. I guess that's as far as lab testing has gone for each.
As far as I understand MRAM has unlimited endurance just like SRAM/DRAM have.
Evan