I2S DAC and the SX

PunMaster

Hello. I am trying to connect a MAX5556 stereo DAC to the SX48. I am fairly experienced with SX assembly, but completely new to audio applications. I have read the datasheet (found here: www.maxim-ic.com/quick_view2.cfm/qv_pk/4850) and some general I2S documentation, but I am having trouble understanding how this interface works. The SCLK and SDATA lines seem pretty simple. They look like a very simple synchronous serial interface. The LRCLK also seems to make sense, it controls which channel my data is going to. But the MCLK line, and all talk of MCLK/LRCLK ratios has me completely lost. Any explanation of this would be great. Thank you.

PunMaster

Bump...

PJMonty

Ryan,

I took a quick look at the datasheet. It all looks pretty straightforward to me. It says the the device can either have data clocked into via an external clock (synchronous) or using an internal clock (asynchronous). You only need to worry about setting the internal clock speed if you want to use an asynchronous serial data stream. That's like normal RS-232 style communications. Ignore that. Just provide the clock yourself via the SCLK pin. You just need to set a bit on the SX to either high or low, and then provide a low to high transition on the SCLK pin via an SX output pin. Lather, rinse, repeat. Just keep setting your bit value followed by a low to high transition until you've transferred all your bits.

Thanks,
PeterM

PunMaster

I have used synchronous serial interfaces a hundred times before, and that part was never the issue. As I said, "The SCLK and SDATA lines seem pretty simple. They look like a very simple synchronous serial interface." Unfortunately, I am still totally in the dark about the other signals. I vaguely know what they are supposed to do (LRCLK selects the channel and MCLK clocks the decoder), but that's all I understand. The datasheet says something about everything needing to be synchronized and that some special ratio between the signals must exist. That right there shot down my initial idea, which was to tie LRCLK low, pulse MCLK with an external oscillator, send data over SCLK/SDATA, and hope to hear something from the left channel. I think all of this complicated signaling is needed to maintain a constant sampling rate and keep the channels aligned. Has anyone here ever dealt with an I2S DAC before? Thanks again. Sorry if my first post wasn't very clear. [noparse]:)[/noparse]

PJMonty

Ryan,

As I mentioned in my post, "You only need to worry about setting the internal clock speed if you want to use an asynchronous serial data stream. " Look at the datasheet and on the front page under "General Description" it says, "The internal serial clock frequency is programmable by selection of a master clock (MCLK) and sample clock (LRCLK) ratio." In other words, as long as you do not communicate asynchronously with it (in other words, you manually clock MCLK as I suggested), you'll never need to handle the ratio stuff. That's all there to let the chip figure out how fast you're communicating to it when you communicate asynchronously.

If you communicate synchronously, it looks like you can do eaxctly as you suggested, e.g. hold the LCLCK line low and just listen to audio on one channel.

Thanks,
PeterM