Are there any results back from Parallax concerning PLL failures?

Peter Jakacki

I recently blew a couple of my chips while prototyping and they displayed the classic PLL failure problem, one even failed to start the crystal oscillator, otherwise everything else worked. Some time ago Parallax was looking into this failure perhaps to see if they needed to make some changes on Prop II I guess. I know that this is not really a failure of the chip design but a simple failure that is common to most overstressed chips.

What I would like to know is have Parallax discovered the mechanism behind the failures and is there anything we can do at the pcb level to make it less sensitive to such failures?

Just from my observations I have the lores pic of the prop die (is there a better one?) which I have traced through as best as I could to see if I could identify the areas. I noticed the concentric rings which I guess are VSS and VDD distribution buses but there are at least another 3 buses which may be I/O VDD and VSS. The oscillator and PLL seem like (logically) they are either near the reset circuit/band-gap ref (bottom left center).

*Peter*

P.S. I have attached an overlay of the die against the pinouts. It looks like the correct orientation.

Post Edited (Peter Jakacki) : 5/30/2008 11:32:13 AM GMT

simonl

If I remember correctly; it's something to do with inductive loads, and they suggested buffering (I think...).

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Cheers,

Simon

---

www.norfolkhelicopterclub.co.uk
You'll always have as many take-offs as landings, the trick is to be sure you can take-off again ;-)
BTW: I type as I'm thinking, so please don't take any offense at my writing style

parts-man73

Look at this thread

http://forums.parallax.com/showthread.php?p=719773

look particularity at the 7th post in this thread, Paul Baker gave some good tips and theory.

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Brian

uController.com - home of SpinStudio - the modular Development system for the Propeller

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Erik Friesen

You probably have much more experience than I, but I blew quite a few prop chips when I first started using them. I got tired of it and started being real careful wearing a static strap when I soldered them in (last) and buffering my inputs with 500ohms+. Typical failure for me was blown single i/o pins. I had one failure when the mcp3208 got zapped(from not good enough buffering) and took the prop with it somehow. One got it with an accidental 12 volt probeing.(immediate death).

Fred Hawkins

I spent the afternoon looking into this and upon a closer examination I think I have found your answer.

BTX

Fred.
Do you mean it is caused by terrorist attack to the PLL ?

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Regards.

Alberto.

Peter Jakacki

LOL.

No, that's not a terrorist attack, it is actually jumpy Israeli jet fighter pilots who react before they finished saying "PL..."

*Peter*

Fred Hawkins

BTX said...
Fred.
Do you mean it is caused by terrorist attack to the PLL ?

Alberto,
In case you missed it, here's the video http://www.youtube.com/watch?v=1uwOL4rB-go

Peter Jakacki

Oh, ok, then there is no need to take it seriously I guess as it's just a dummy threat

*Peter*

rjo_

Peter... Peter... Peter...

Fred...Fred... Fred...

and ALL ships at sea.

This thread has it all... a great problem, great graphics, and unsurpassed humor. I just don't want to see it die.

You guys are engineers. I'm not. So, I am NOT going to try use the right technical terms, but I'll bet you a bottle of your favorite that there is a resonant condition that makes the PLL go pop...that's my intuition.

AND if my intuition is holding up, right before the PLL goes pop...if you could listen carefully enough you would hear the electrons saying... "oh...........oh....Oh.. OH.AHHHHHH (...) ouch."

What makes this reasonable to my brain is the fact that while electricity travels at close to the speed of light...electrons don't. It doesn't seem reasonable to me that the excess energy is being transmitted by "more" electrons... rather the electrons in the circuit must be picking up extra energy. Imagine a one dimensional cyclotron... in which (during each resonant interaction) the electrons gain energy. The frequency would be determined as an inverse function of the average axial distance between electrons, which should be a constant.
How would this translate to an experiment or a solution? That's engineering.


Rich

BTX

Fred.
I can't stop to laugh, after I see the video... hahaha. It's great !!
I never saw they before.... very good show.

Anyway, although it's too funny, I'm waiting for somebody from Parallax, that answer to Peter.
I've too many propellers in the "streets", and I'm a bit afraid now, although I did never can to fried any PLL.
I would like to know too, exactly, ...why.
Really, I don't want to be a victim of Achmed.

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Regards.

Alberto.

Ken Peterson

I imagine of all the subsystems on the Propeller, the PLL has to be the most sensitive to being out of tolerance, since it experiences the highest frequencies within the chip. So if something happens to the chip in general, I would expect the PLL to be the first thing to go. The rest of the subsystems on the chip may not be as sensitive to a similar degradation.

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simonl

LOL

But back to the thread - Parallax answered (as Parts-Man said) in http://forums.parallax.com/showthread.php?p=719773

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Cheers,

Simon

---

www.norfolkhelicopterclub.co.uk
You'll always have as many take-offs as landings, the trick is to be sure you can take-off again ;-)
BTW: I type as I'm thinking, so please don't take any offense at my writing style

Peter Jakacki

simonl said...
LOL

But back to the thread - Parallax answered (as Parts-Man said) in http://forums.parallax.com/showthread.php?p=719773

Yes and no. The reason I say no is that I am well aware of poor design practices or more correctly I am aware of good design practices and implement them in my designs. Of course I can still make mistakes but I am not aware of any of the problems that Paul mentioned. There were no inductive loads in my circuit but there is a 32V rail which goes to some drivers but of course the grounds are localized. The CPU is well away from the power drivers which have their own supply and ground planes and traces.

I was more interested in what does actually happen when the chip is stressed so as to fail in this manner. Knowing this helps to formulate a more complete and comprehensive plan for designing with the Propeller, being aware of the pitfalls and the failure mechanisms involved. Bars on windows for instance are a good protection - against break-ins - but not against mosquitoes. I've never had a design failed before so it must be a mosquito problem!

I'm quoting Paul's reply below for easy reference.

*Peter*

Paul Baker said...

OK, since people keep asking, I'll try to explain what's going on more fully and precautions which can help lessen the likelyhood of PLL failure. Inductive flyback and ground loops are the predominate causes for PLL failure. This is not a "poor design" on the part of the Propeller, rather something is done by the operator in thier design which causes abnormal conditions, and the PLL happens to be the weak point (if we strngthened it, the failure would occur somewhere else).

If you are driving any coils, such as in a relay, be sure the coil has a reverse biased diode to sink the collapsing field and doing it on the transitor driver too doesn't hurt. Failure to do so will dump the charge onto the supply, into the Propeller and fry the PLL.

Ground loops occur when two points which are supposed to be an equal potential (such as the ground connections on two chips) are not the same potential. First, while it not directly related, all chips whose current consumption can rapidly change (such as anything containing logic gates, ie all digital chips) should have a bypass capacitor, this helps to remove noise on the power supplies. Second the ground connections need to have as little resistance as possible, this means wide traces (This should be done for power too), and ideally the ground is a plane (and in 4+ layer designs power are planes as well). Take a look at the back of any Parallax product, see how the entire area is filled with copper? That is the ground plane, and it is there to minimize the potential for ground loops.

Also ALL propeller supply pins should be connected to the other supply pins at the Propeller (Vdd to Vdd, Vss to Vss), not doing this can cause a ground loop inside the Propeller. And never, ever use the Propeller's supply pins as a pass through (power supplied on one pin in turn supplies other components on another power pin not externally connected to the first pin, this is true for Vdd and Vss). You will be creating a ground loop if you do this.

Also in situations where multiple boards are connected together the common ground connection should be as hefty as practical. There's also issues with seperate AC powered boards, they should get thier power from the same outlet if possible (since ground loops can happen through your house/office's electrical system as well).

Lastly there is a phenomena with how current flows through the ground plane, it follows the path of the supply trace on the other side. Strange, but true. You should avoid breaking the path it wants to follow with any traces since it has to go around it, or at least minimize the distance it has to detour.

We follow these design rules and thus far have never had a design where the PLL failed.

Mike_GTN

I thought that the Youtube clip was actually Mr Bush, Mad and takes people and countries with him. I don't really know if he has had any personal PLL failures, just mainly PLO ones. Feel sure his heart is in the right place, just that I would not trust him with the big red button (That said do not push)

cgracey

In the parts I've checked that suffered PLL failures, the PLL was actually still running fine, as evidenced by the power-supply signature. It was the multiplexer logic AFTER the PLL that had died. I don't know why this happens yet, but we will be reviewing the local·VSS/VDD power routing to look for any weak points. Something is popping under electrical over-stress, for sure. I have never experienced this failure, myself, and I've worked with quite a few Propeller chips, but mainly on Propeller Demo Boards, so that Demo Board seems to be a safe platform. I would guess that its tight VSS/VDD routing is what keeps those Propellers safe.

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Chip Gracey
Parallax, Inc.

Peter Jakacki

Thanks for that feedback Chip.

I reviewed my pcb and found maybe two areas where I could have problems so I will make changes in this area for the production pcbs as these are only protos mostly to check the functionality. This design has an up-converter to +32V in the lower left hand corner which when overloaded (which happened) can draw some current. Part of the ground current would flow along the left through section A (attachment) and then through section B which means that it passes through the Propeller's ground pins. Of course this is not the primary current path but still it is a path. The solution is to isolate the ground at section A and although not as critical for different reasons the ground at section B.

This board really begs for more than 2 layers as it has to handle large currents so the final may indeed be four layer.

We all know and it's common sense that anything that is overstressed is going to give, so I don't blame the Prop Chip [noparse][[/noparse]pun] as anything to try and bolster-up in one area will just fail in another area, but where?. Better to know where the weak point is and then it's just plain science.

I have attached an image of the offending pcb for your information.

*Peter*

Fred Hawkins

Offtopic aside to Parallax. It would be NICE to have a picture like Peter's PCB Grounding.png for the Protoboard.

Edit, on topic. Found a discussion of stray voltages in a system in this pdf: http://focus.ti.com/lit/an/slva271a/slva271a.pdf·I guess TI was lucky because it was visible; they might might not have noticed it otherwise unless the stray voltage killed their chip. It's interesting that they mention that the effect is linked to 'time multiplexing'. The prop is all about multiplexing...

Post Edited (Fred Hawkins) : 6/5/2008 6:07:57 AM GMT

BTX

Hi Peter.
Do you have the 1uF ceramic capacitor, between pins 5 and 8, like the "demo board" have ?
I can't see it in your PCB, I always place it very close the pchip pins...
I can see only one, but in pins 17 and 18, I always use a 0.1uF there.
Maybe that could be a great reason for fails.

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Regards.

Alberto.

cgracey

Fred Hawkins said...
It would be NICE to have a picture like Peter's PCB Grounding.png for the Protoboard.

I've asked Thomas, our PCB engineer at Parallax, to post high-def images of the top and bottom copper layers of the Propeller Demo Board to this thread. This way, all can see what tightly-wired power looks like.

By the way, I really liked your video showing what causes PLL failure. That's·much more·dramatic imagery than·we glean from our·own tools. It's like a 'Fair and Balanced' approach to·failure analysis.

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Chip Gracey
Parallax, Inc.

Fred Hawkins

Chip Gracey (Parallax) said...

Fred Hawkins said...
It would be NICE to have a picture like Peter's PCB Grounding.png for the Protoboard.

I've asked Thomas, our PCB engineer at Parallax, to post high-def images of the top and bottom copper layers of the Propeller Demo Board to this thread. This way, all can see what tightly-wired power looks like.

By the way, I really liked your video showing what causes PLL failure. That's·much more·dramatic imagery than·we glean from our·own tools. It's like a 'Fair and Balanced' approach to·failure analysis.

Thanks, now all I need to do is to buy a Demo board. (Mostly I hoping for multicolored view of the layers of the Protoboard, which has always stumped me -- is this hole the source of magic smoke or this hole? Having a pictorial schematic that organizes my grasp of that board would do wonders for my confidence.)

Glad you liked my gif (finally used my animator from Ulead). The idea went like this: it would be cool to animate an explosion, then·an explosion·needs a terrorist, then remembered Achmed's "I·kill you" and couldn't stop laughing all afternoon. My better half suggests that Achmed's line may become an in-house Parallax meme much like in-home around here. Maybe not, though, there's always "seven".
·

Thomas Bauer

Here are some pictures of the routing on our Prop Demo PCB. There is also a picture from the Prop Proto PCB.



-Thomas

Fred Hawkins

@Peter, what software makes your png? I like that the layers are transparent.

@Thomas, thanks. (Now bigger, and with the prop plug terminal, please. Or maybe should I be greedy and go for the whole board?)

Peter Jakacki

Fred,

I am using Protel99SE and I configure it for transparent mode which makes it a lot easier to edit. I just adjust the colors a little so features are not obscured.
Almost any program creates a png though. Here's one way of doing though with freely available tools. Copy your screen to the clipboard and then import clipboard in Xnview, crop and save as filetype "png". Whereas GIF is a licensed filetype and is limited to 256 colors, PNG is non-lossy like GIF and ideal for handling graphics but offering far more compression than GIF. Both handle transparency but with PNG it's adjustable although IE has a bug handling it.

@Alberto, there is always at least one 0.1uF right next to the Prop or under it. The 1uf is part of the regulator module "SM7805+3" and as this "bulk capacitance" is not useful for transient response it does not have to be right next to the Prop. In fact the 1uf is mainly for the LDO regulator as it needs it to remain stable especially when there are sudden (relative to the regulator) extra load demands (i.e. Prop switches to XTAL+PLL16 mode from RCFAST etc). Having bulk capacitance in a circuit is always a good idea, expect it can be placed a little further away if necessary.

In saying all this there is no way that the omission or incorrect placement of a decoupling capacitor will cause the chip to fail. The chip may malfunction due to the supply glitches but it won't cause the silicon to fail. As Paul and Chip mentioned it usually is when you have excessive currents flowing through the ground pins of the chip, in my case it is remotely possible but I am more inclined to think that one of the I/O pins copped a hammering straight from 32 volts. So it's not a pcb layout problem, just one of those things that can happen when you have all those volts and amps lying about while prototyping.

I have included some other partial pcb layouts as examples. These are not perfect examples, just prototypes, but they give you some idea of the variations.

BTW, I'm happy to post specific layouts and schematics or even some complete ones for educational examples if that helps anyone. I might post them up and maybe they can be linked from the wiki?

*Peter*

Praxis

I have to admit I was a little worried by the subject of this thread particularly in relation to Peter's comments as his board layouts look good. The comment about possible hits to 32V is probably true and puts my mind to rest.

Anyway for those interested here is the PCB layout we did.

BTX

Hi.
I usually use this configuration without any damages of the chips, although some wires in the GND and VDD are not totally correct like (Paul suggest before and Chip said).
My LED screen has 17 propellers running many hours from the past October, never had fails. neither PLL's.
Like you, Peter said...maybe it is caused by (copped a hammering straight from 32Volt)... I don't know ...but with this PCB also all, works fine.
There are not ANY "inductors" in the circuit, and absolutely not excessive currents flowing through the ground pins of the chip.
This is one piece of the boards. (Image "b.png").

And I talk about the 1.0uF capacitor, NEAR the VDD and GND pins, because that:
(Images 1.jpg and 2.jpg)

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Regards.

Alberto.