B port Propeller ?

jazzed

Parallax,

Any luck with the Propeller with port B (64 total I/O pins) enabled?
Is the product in the roadmap at all?

Thanks in advance.

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
jazzed

Mike Green

The only Propellor that's been actively discussed is the Prop II. I think there was a comment about no Propeller I with port B because that would take resources away from the Prop II with no significant benefit. Port B doesn't really exist in the current Propeller chip and it would take a chip design and all the testing steps to get it without the benefits of the Propeller II design which would have 64 I/O pins anyway.

KamPutty

Is there any status on the Prop2? Any info that can be shared?

~Kam (^8*

Mike Green

For what it's worth, my comment was simply my memory of an "official" comment from Parallax, probably Paul Baker.· It's in one of the threads on the Propeller II.· There have been plenty of clear answers, maybe not satisfactory for all, but certainly clear.· The trick is in finding them among all the other clear answers.

The status of the Propeller II is that it'll be ready when it's ready and there won't be any further communications on it until it's ready.· That was the last official status.






Post Edited (Mike Green) : 5/27/2008 11:50:30 PM GMT

mirror

Just a quick note! Hopefully not too off topic,

What I would prefer to see (and would fit in the current architecture), is to scrap the current assignment to ports INB, OUTB, and DIRB. They could be changed to become cog configuration registers. One of the configurable items would be to have a bit (or maybe two) that selects whether the INA, OUTA and DIRA registers apply to port A or port B. There are many benefits to this change:
1) The current requirement for setting the carry flag to determine wether to use Port A or Port B for WAITPNE and WAITPEQ could be avoided - I'm sure this one is going to cause some tears in Prop II!
2) A cog is then limited to conveniently being able to only control 32 port pins (on either port) - but does any one really care about this limitation?? Since it would be configurable. If you really wanted to you could access all 64 pins from one cog, it would just be a bit harder.
3) Aside from the configuration register, there would be two free registers!! The mind boggles at what could be added.
4) How about using one of the (new) free registers to be the input equivalent of the current video output register! (video sampling here we come)
5) The configuration register could be used to used to select alternate instruction variations. eg: DIV and DIVS could be overlaid on MUL and MULS. DEC could be overlaid on ENC.

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔

Bob Lawrence (VE1RLL)

Paul Baker said...
It has been completed, but the LVS utility chokes on the design. Until we can resolve this issue, the P8X32B (Prop-1 w/ 64 I/O) will remain on the shelf

Try this discussion:
http://forums.parallax.com/showthread.php?p=722541

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Aka: CosmicBob

ErNa

As I already mentioned: it would make sense to have "burried" I/O. This would allow the cogs to communicate very fast and we could use the same protocol to communicate between different chips via port A.