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Propeller nybble-serial interchip communications speed - Page 2 — Parallax Forums

Propeller nybble-serial interchip communications speed

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Comments

  • Ken PetersonKen Peterson Posts: 806
    edited 2008-04-22 11:06
    IC design is one thing I've never done. Good luck with that. Is there any speculation yet about a launch date for either chip?

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  • stevenmess2004stevenmess2004 Posts: 1,102
    edited 2008-04-22 11:30
    Are there going to be any changes to the interpreter for the 64 pin version or is the plan to keep it the same?
  • simonlsimonl Posts: 866
    edited 2008-04-22 11:47
    I'd expect everything to stay the same; only we'll be able to use INB, OUTB, & DIRB.

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    Cheers,

    Simon
    www.norfolkhelicopterclub.co.uk
    You'll always have as many take-offs as landings, the trick is to be sure you can take-off again ;-)
    BTW: I type as I'm thinking, so please don't take any offense at my writing style smile.gif
  • hippyhippy Posts: 1,981
    edited 2008-04-22 12:23
    The interpreter and bytecode seems almost certain to be the same for the 64-pin Prop I but will have to change for Prop II because 16-bit words are currently used as address pointers in the Object Method Tables and as return addresses on the stack, for 256KB addressing they will need to be 18-bit. Conveniently though, with everything aligned on long boundaries, the 18-bits can be right-shifted to fit 16-bits and back again with no errors introduced.
  • Paul BakerPaul Baker Posts: 6,351
    edited 2008-04-22 17:51
    Ken Peterson said...
    IC design is one thing I've never done. Good luck with that. Is there any speculation yet about a launch date for either chip?

    wrt Prop-2, it's too early to have any projection other than the·vague timeframe given already. Prop-1B we can't speculate either because there is a roadblock preventing progress.

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    Paul Baker
    Propeller Applications Engineer

    Parallax, Inc.
  • hinvhinv Posts: 1,255
    edited 2008-04-22 20:08
    What part of IO-B is not there? I thought that it was all there except the pins, and people were using it to pass data between cogs.
  • Ken PetersonKen Peterson Posts: 806
    edited 2008-04-22 20:29
    hinv: We're talking about a possible new version of the Prop I with pins added for IO-B

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  • hinvhinv Posts: 1,255
    edited 2008-04-22 22:56
    I guess I should have been more specific. Doesn't the current prop have all of the logic for the IO-B except pins to connect to?
  • Mike GreenMike Green Posts: 23,101
    edited 2008-04-22 23:03
    Not really.· The memory locations for INB / OUTB / DIRB are there, but none of the special hardware exists.· Try setting DIRB and OUTB, then see if you can read it from another cog using INB.· You'll find that it doesn't work.
    ·
  • Paul BakerPaul Baker Posts: 6,351
    edited 2008-04-22 23:06
    It's not the design its the design tools, in order to verify that the schematic matches the layout you have to run a utility called LVS (Layout verses Schematic). Without this tool we cannot not justify paying many thousands of dollars to fabricate the chip because we have no indication of the "correctness" of the design wrt to the schematic. This tool when run on the design crashes the computer, and until this issue is resolved we cannot verify the design and it will sit on the shelf until we can get it to verify. And before we start getting "are we there yet" posts, we have been in this spot for many months now, and likely will for a while longer.

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    Paul Baker
    Propeller Applications Engineer

    Parallax, Inc.

    Post Edited (Paul Baker (Parallax)) : 4/22/2008 11:13:33 PM GMT
  • Ken PetersonKen Peterson Posts: 806
    edited 2008-04-23 12:22
    So perhaps you're stuck until you get the next revision of the LVS tool? I won't bug you about it anymore! [noparse];)[/noparse]

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  • Beau SchwabeBeau Schwabe Posts: 6,568
    edited 2008-04-23 13:30
    Ken Peterson,
    ·
    I'm going to lean toward human error... the LVS tool is fine, granted it has limitations, but they are the sort of limitations that I have seen across the board with other LVS tools.· If you know and understand the various quirks about the tool and what it's trying to tell you then most if not all f your problems will go away.· Nothing is waived; all layouts must pass with 100% schematic correspondence.

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    Beau Schwabe

    IC Layout Engineer
    Parallax, Inc.
  • Ken PetersonKen Peterson Posts: 806
    edited 2008-04-23 13:49
    I've never done chip design before and this is all very interesting. I'm sure there are other forum readers who are also interested in learning more about the process.

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  • Paul BakerPaul Baker Posts: 6,351
    edited 2008-04-23 18:11
    From what I understand (I haven't used a professional IC layout program since Cadence in college) it requires some massaging to get it to work correctly. What I recollect from a conversation with Beau, it takes fiddling with some script files to get things in a shape the LVS likes to see them, but that the required changes aren't always obvious (iow it can be a bit of black art).

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    Paul Baker
    Propeller Applications Engineer

    Parallax, Inc.

    Post Edited (Paul Baker (Parallax)) : 4/23/2008 6:19:31 PM GMT
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