New chip with four 400 MIPS cores!

Leon

XMOS, founded by David May who designed the Inmos Transputer 25 years ago, has developed a four core chip with each core delivering 400 MIPS. Each core also has 64 I/Os. Volume cost will be $10 each.

http://www.xmos.com/

I was one of the first Transputer developers, I might be able to get some samples out of them.

Leon

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Amateur radio callsign: G1HSM
Suzuki SV1000S motorcycle

Post Edited (Leon) : 4/15/2008 10:47:06 AM GMT

mikestefoy

It gladdens the heart of an old Englishman to see the name of the Transputer, and David May mentioned, and alive and kicking.

Mike

Ale

Looks nice but it comes in a very unfreindly 512 ball BGA package :-(. Their 1 XCore version comes in a more friendly QFP version, but only 16 I/Os... a bit limited

Post Edited (Ale) : 4/15/2008 11:01:43 AM GMT

stevenmess2004

Looks like it will be roughly equivalent to the propII. Chip, when will it be ready? The competitors are catching up!

It looks like it would be all right but it only has 8 registers per thread. Now if you have 8 threads than the MIPS/thread is 400/8=50 which is about a third or what the propII should do.
And it has too many pins and they can only do 4mA. The prop can do 10x that.

Enough bashing it. Some nice things about it
-Three operand 16 bit instructions. Nice and compact.
-40 32bit timers. PropII will probably only have 32 :-(
-Can fetch 2 16bit instruction / cycle
-Buffered input and output
-XLink looks interesting. Especially off-chip option

Just a thought. Wonder how hard it would be to make the PropII into an emulator for this using a LMM?

heater

Now there is one idea from the Transputer and now XMOS that I would love the Prop to have, high speed serial links between CPUs (cores, cogs whatever). Especially if they could be brought out of the chip to neighbouring chips.

Do this only betwen neighboring COGS, matrix fashion, but allow cogs on the edge of the matrix to either drive the serial links out to I/O pins or connect back round to COGS on the opposite edge of the matrix.

Adapt the existing serial shifters in the video logic of each COG to optioanlly do serial links.

Then get ImageCraft to produce a parallel C compiler[noparse]:)[/noparse]

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
For me, the past is not over yet.

hippy

I do have to agree; 'sendtx' and 'waitrx' PASM opcodes as a simple means of doing fast inter-chip comms ( and inter-Cog via INA/OUTA loop-backs ) would be superb. Not sure how it could be added to the Propeller but simpler the better in terms of not overcomplicating the design. Maybe 'waitvid' is good enough for output and we just need a 'waitvidin' ?

stevenmess2004

Yes, something like a waitvidin would be great. But don't forget that we want a clocked version and a non-clocked version. The propII has enough I/O that some pins could be dedicated to communication between cogs if you wanted to. If we had the waitvidin it should be possible to do data transfers upto the same data rate as the cog-hub does in the current cog.

hippy

stevenmess2004 said...
Just a thought. Wonder how hard it would be to make the PropII into an emulator for this using a LMM?

Possibly, but the instruction decoding looks complicated and there seems there would be a lot of complexity in handling the I/O types and XLink.

The XS1-G does serve a purpose in highlighting the simplicity of design and consequential ease of use of the Propeller in comparison. I think I'll take the easy option

heater

Thinking about the Prop II something does not add up for me. If there are 16 COGs it makes little sense that they all have video hardware. Who is going to drive 16 displays from one chip ? Which would require a bucket load more RAM than is available anyway.

But we do have the philosophy of regularity, all COGs should be equal. So it make a good argument that the video shifters should be enhanced a little for communication purposes, shift in, shift out possibly some NRZ/NRZI encoding etc. Then a few extra traces on the chip and gates to direct links to neighboring COGS or I/O pins.

Given 16 cogs, imagine them as a 4 by 4 array. Links go/left right up/down. Top row would loop to botom row and left column loops to right column thus keeping to the regularity rule.

Save COG zero which would boot up from a link on an I/O pin. In fact maybe like the transputer all COGS should boot from a link in this way all cogs could be started with PASM code with no need to access HUB RAM.

If I remember the transputer would listen to all of it's links on start up and boot from which ever recieved code first.

This would make all COGS more equal.

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
For me, the past is not over yet.

stevenmess2004

I think one of the reasons they didn't mind putting a video generator in each cog is because they take up so little room. If you look at the die picture of the propeller the timers take up a tiny amount of room compared to the rest of the cog.

If you want a 4x4 array than look at the seaForth or the tile64 (or something like that). The problem with an array is that it becomes hard to share a large amount of memory.

heater

Ah, but I'm not talking about a physical array layout on the chip. Only that the existing video shifters serial inputs and outputs be carried over a few traces to the appropriate cogs to make the logical array connectivity, plus some extra gates to switch between COG to COG or COG to pin routing. Would that take up so much chip real estate ?

But now we need extra shifters to receive data. Or do we ? If all the shifters used for communication were running in synch then they could shift input data in one end whilst shifting output data out the other. So a 31 bit shifter could simultaneously send and receive 32 bit words.

It's nice to ponder all these possibilities but Prop II is up to Chip and I'm feel sure he has some surprises for us.

As for seaForth and tile64, may be one day I'll have the opportunity to lok into it but I've just invested a lot of time in getting up to speed with the Prop and I love it.

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
For me, the past is not over yet.

stevenmess2004

Fast cog-cog communication would be nice but it gets hard to manage. I think that Chip is planning to put in a mode that transfers 8 longs to/from the hub in one hub access. This should allow pretty fast access so I think that a dedicated interface becomes a moot point.

8 longs every 16 clock cycles would be faster than a serial port running at the clock speed anyway and have a lower latency.

As mentioned above though one of the really important thing about the propeller is that it is
1. relatively simple to understand and program
2. easy to interface with. Sure, the other chips may have more raw power, but try to hook a led up to one on a breadboard.

kuroneko

heater said...
Thinking about the Prop II something does not add up for me. If there are 16 COGs it makes little sense that they all have video hardware. Who is going to drive 16 displays from one chip ? Which would require a bucket load more RAM than is available anyway.

I find the video h/w useful to talk to e.g. external memory (like the Hydra SRAM card).

hippy

I think it would be acceptable to have inter-Cog and inter-chip links different. I believe Chip would want to keep the design simple and clean.

Like Locks, it would be possible to have N internal shared FIFO's and any Cog can wait on/write to any FIFO, any Cog can wait on/read from any FIFO, N => number of Cogs makes sense. That would be flexible in allowing limited tiling or single Cog's with multiple links in/out as design requires. It's beauty is it's easy to see/explain how it works. FIFO could be as little as 1-deep. Chip may argue that via-Hub block-transfers are just as useful, more flexible, the counter argument is 'waitfifo' is simpler and easy to use with less code.

Waitvid can be used as an enhanced SPI output, and all that's lacking is the equivalent to read a video stream.

I think we're talking Propeller Mk III here, but we don't knows what magic Chip is going to include in Mk II.

yerpa58

I just threw away my old Transputer manuals. I agree that it was a very nice clean innovative design. However, I remembor sitting in a developer's meeting and hearing the audience boo loudly when the white space indentation "feature" of the programming language was discussed! I'm not sure why the chip never really took off in the market. I think it might have been a little ahead of its time. I also concur that a video shift register input might be very nice for multi-chip prop applications, and that the relative simplicity of the prop is an outstanding feature.

heater

Oooo How could throw away such treasures?

White space indentation is a pain, skip a few spaces or a tab and all hell brakes loose. So many times I've sworn at cut and paste dong that.
More seriously the Occam language to which you refer whilst being truely wonderfull just was not C. Same debate we have about spin and the propeller. Although parallel C for the Transputer did turn up from third parties.

As for why it did not take off. Well the T8000 launch in London that I attended totaly lacked the pizzaz of the Intel launch of the 860 chip about the same time. Nobody quite knew what the transputer was for, I think, and the marketing did ot tell you. Perceptioned seemed to be it was aimed at highly parallel super computer stuff so embedded engineers did not look into it.

Strangely enough though at that Intel 860 launch exhibition/conference many of the exhibitors showing off products using the 860 for floating point number crunching speed were also using transputes for the interconnects !

I nearly got the transputer into one design that needed three seperate processors for security reasons. It was a perfect fit except for the power consumption. That finally went with thee Intel 8088s.

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
For me, the past is not over yet.

Leon

The main problem was that Inmos never got the second-generation T800 to work properly. That would have been streets ahead of everything else at the time.

Leon

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Amateur radio callsign: G1HSM
Suzuki SV1000S motorcycle

stevenmess2004

How many transputers did they make and how hard are they to get now?

pharseid

· I think I have a couple of ISA transputer boards and maybe a loose chip or two somewhere. But I really wouldn't advise taking up a obsolete processor line. I think Analog Device's Sharc processor (essentially a DSP transputer) and maybe even TI's similar chips may still be in production. And they both have higher communication speeds than the original transputers. I would look at those before I looked at the transputer. (Although if I remember correctly, somebody was talking about implementing the transputer on an FPGA a while back, which would pretty much make it immortal.)

-phar

heater

A major point for me and I suspect many others here is that XMOS, seaForth and tile64 etc are not Parallax.
The propeller is here and now complete with a free development environment. For a few euros I can get a Prop chip in my hand from a local supplier and half an hour later it's up and running with almost no support circuitry required. All technical info is available.

If XMOS and the like would provide a 100€ protoboard and free compiler I'd be on them like a shot. I imagine that is not going to happen any time soon as they want serious volume with big customer "partners". They have to get back that 16M venture capital which is a lot of chips and a lot of expensive development tools.

I would love too see compainies like XMOS have an eye on us hobbyists, students an other small guys. I'd also like to see Parallax making it up to the industrial volume market.

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
For me, the past is not over yet.

pharseid

· Yeah, I'm surprised this thread hasn't been moved to the Sandbox, as it isn't about Parallax products. It's also a neverending game to be looking at the Next Big Thing, because, of course, there will continue to be NBT's until the ability to scale logic runs out. Of all these, the only processor that really seems interesting to me is the Tile64, because it has a DDR2 interface (or several). It strikes me that if they ever do a Hydra II, they need to implement it with a processor that supports some form of DRAM, so they have enough memory space to compile Panda3D or something else like that. With multiple DDR2 interfaces, you could have one memory bank for code, another for textures, another for the z-buffer, and so forth. And tons of processing power. And the end users wouldn't have to buy their compiler, they could program it in Python.

··But I'm wondering if they sold enough Hydras to make a Hydra II a possibility?

-phar

hinv

Yes, chasing the NBT can be quite exausting, especially there is no were near the help you can get on this forum for any of them I have seen. The SEAforth chips that have just come out on an initial run, so it is a bit early to tell, but less than 1 post/day on the forum is not a good sign. It is interesting to see more discussion on the SEAforth chip on forums.parallax.com than on ww.intellasys.net/phpBB, ....ok, maybe I am exaggerating a little
I would think that if there was a Hydra II, it would use a PropII. I don't think the retro game programming hobbiest market can afford the Tile64 also. As discussed elsewhere, the PropII w/64 io's will have enough pins to add external memory, not a real memory bus, but certainly better than the Extreme512 card can do, and enough for a frame buffer.
If you have seen what baggers has been able to do with the current propeller on his PropGFX light, it will be truely amazing on 8 times the processing power and enough memory!
I could not agree more with heater. I used to play with the HC11 back when it just came out, but since then, I had moved on to bigger computers. It was quite refreshing to see that you could just wire things up like I used to do, but with a current chip. When my wife had gotten me "What's a Microcontroller" kit for Christmas 2006, I was rehooked! It really was a refreshing experience, and then my propeller demo board really topped that. You have to hand it to parallax for their educational approach to microcontrollers/computers. It may not be as profitable as selling tens of millions of ARMs or AVRs, but from what I have learned about Chip, it is more about passion than profit. Kudos to parallax!

Doug

ErNa

I worked with the Transputer for some years an still own them. And I NEVER threw away documentation. It's all well kept for my museum I miss the time of occam, indentation and simple ? and ! to communicate. But now, the propeller is here and he was not dedicated to control combat aircrafts. That will give him a future.

Gadgetman

ErNa said...
I worked with the Transputer for some years an still own them. And I NEVER threw away documentation. It's all well kept for my museum

Swap you one kit for a Cambridge computers Z88 with manual?



▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Don't visit my new website...

tripp

How many transputers did they make and how hard are they to get now?

Look here: http://cgi.ebay.com/3-Rare-Vintage-Inmos-Transputer-NOS_W0QQitemZ220223319130QQihZ012QQcategoryZ4193QQssPageNameZWDVWQQrdZ1QQcmdZViewItem

/Tripp