Question on PASM WaitCnt
hippy
Posts: 1,981
waitcnt waits until a match between CNT and a register, and CNT increments per cycle, four times per instruction, but what happens with the following ...
Where an odd number of cycles are waited ? Is waitcnt a special case where it executes every cycle ?
I'm guessing it is, in which case waitcnt can be used to insert extra cycles in other instruction sequencing, right ?
What about waitpeq and waitpne; do they always take 4 cycles or do they also continue execution on the cycle the pin matches the target ?
mov timeout,CNT
add timeout,#101 ' Odd number of cycles
waitcnt timeout,#0
Where an odd number of cycles are waited ? Is waitcnt a special case where it executes every cycle ?
I'm guessing it is, in which case waitcnt can be used to insert extra cycles in other instruction sequencing, right ?
What about waitpeq and waitpne; do they always take 4 cycles or do they also continue execution on the cycle the pin matches the target ?
Comments
PASM instructions do NOT execute every forth clock - it's just that they all (well most of them) happen to take 4 clocks cycles to execute.
In the case of waitcnt, the cog will wait until the CNT is an exact match, and then start running again - which could take any number of clocks (well up to 32 bits). (NOT just a multiple of 4). The manual says that these instructions all take 5+ cycles.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Every instruction starts on a tick and for the majority of instruction they take four ticks and something particular happens internally on each tick, other instructions execute for however many ticks ( such as until a count matches ) they need and then there are a number of ticks before it finishes and the next instruction starts.
So for the Propeller, everything synchronises to the tick, not like other processors which synchronise to every four ticks.
Thus two identical Cogs, initially in synch and toggling an output simultaneously in response to some input ( ie waitpeq ) could get one tick out if one got its input a cycle later than the other.
Mind you, it is possible to use waitcnt to get the code in all 8 cogs·perfectly synchronised, but if you then use all 8 (synchronised) cogs to access hub memory, it's pretty much a case of "lucky dip" as to which cog will get the first access. Thereafter the cogs will access the hub in ascending order - every 2 clock cycles per cog.
How to get 80MHz sampling and all the rest suddenly makes a lot more sense to me. Ta.
http://forums.parallax.com/showthread.php?p=721428
Hub access all occur on particular and regular ticks, so to ensure ideal Hub access at the sweet spots, ensure every Hub access falls on every 16 ticks.