I'm fairly sure that they are set to 0. However, I'm not sure because I can't find it in the manual or data sheet anywhere. Normally it shouldn't be a problem because you would do an instruction that affects the flags before using them but you may have a reason.
It's pretty simple to write some code to figure it out. I'm curious why you would ever want to use an unset flag, I cannot comprend what you could use it for.
I tried this out. They're both clear. Z=0, C=0. This information might be useful if you directly enter a loop where flags depend on the previous cycle.
Paul Baker (Parallax) said...
It's pretty simple to write some code to figure it out. I'm curious why you would ever want to use an unset flag, I cannot comprend what you could use it for.
The point is that every processor I dealt with so far informs me in its data sheet what the initial state of registers and flags is, where execution starts etc. Yes, I could write some code, but that doesn't guarantee that I will always get those values.
Gotcha, yes the cog is cleared before the contents are loaded, so all SPRs (except PAR) will be 0 at the start, this evidently is the case for the flags as well. Sorry if you felt the documentation is lacking. I'll be happy to give you (or determine) any other behaviours of the chip you want to know and hasn't been disclosed.
Propeller is unique[noparse]:)[/noparse] Sounds like a check box item on a supplier quality survey.
There is nothing wrong with due-dilligence, but since the flags are set as a
result of conditions that you want to test deterministicly, the point is curious.
The only functional reason I would care is in doing a "power on reset" value
check as is typically done for complex ASICs, but less so for FPGAs. Of course
there are other methods for ASIC screening ....
Paul Baker (Parallax) said...
Gotcha, yes the cog is cleared before the contents are loaded, so all SPRs (except PAR) will be 0 at the start, this evidently is the case for the flags as well. Sorry if you felt the documentation is lacking. I'll be happy to give you (or determine) any other behaviours of the chip you want to know and hasn't been disclosed.
Paul, These initial condition issues bring up a good point. Do you keep a running list of changes to the manual? (or do you make them directly?) I do have a number of such issues with the propeller manual where most instruction set documentation i've used in the past is more thourough when describing each instruction. I'll be glad to forward things I see. Maybe we have a thread somewhere or you'd like them directly sent?
Yes Jeff Martin is the "product owner" of the manual. He and our editor have been maintaning an excel speadsheet of errata for the next revision. I do not know when they will start the revison other than it will be "months from now", but they occasionally update the errata document people can download.·I am the product owner of the datasheet, and thus far I have been writing my errata (more of a to do list) on my white board since it is still a short list. I do not anticipate getting to any of the items before September when my current major project is tentitvely scheduled for release.
PS dont email jeff please, he's a very busy man. If you've found something, chances are we already know about it, but perhaps we don't. So check the errata document first. If it's not there send an email to me or stephanie lindsay our editor.
Comments
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Paul Baker
Propeller Applications Engineer
Parallax, Inc.
Post Edited (Paul Baker (Parallax)) : 4/9/2008 6:35:01 PM GMT
The point is that every processor I dealt with so far informs me in its data sheet what the initial state of registers and flags is, where execution starts etc. Yes, I could write some code, but that doesn't guarantee that I will always get those values.
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Paul Baker
Propeller Applications Engineer
Parallax, Inc.
There is nothing wrong with due-dilligence, but since the flags are set as a
result of conditions that you want to test deterministicly, the point is curious.
The only functional reason I would care is in doing a "power on reset" value
check as is typically done for complex ASICs, but less so for FPGAs. Of course
there are other methods for ASIC screening ....
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jazzed·... about·living in·http://en.wikipedia.org/wiki/Silicon_Valley
Traffic is slow at times, but Parallax orders·always get here fast 8)
Thank you!
-Stephen, KZ0Q
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PS dont email jeff please, he's a very busy man. If you've found something, chances are we already know about it, but perhaps we don't. So check the errata document first. If it's not there send an email to me or stephanie lindsay our editor.
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Paul Baker
Propeller Applications Engineer
Parallax, Inc.
Post Edited (Paul Baker (Parallax)) : 4/10/2008 1:47:10 AM GMT