I/O cycle timings

kuroneko

When writing an output value to e.g. OUTA, when does the output (pin) actually change in terms of instruction cycles (1-4). Also, when reading from INA, which instruction cycle does latch the value available at the input pin? For the latter, it may well be that the inputs are sampled with the system clock (I simply don't know), if so which edge?

TIA

Post Edited (kuroneko) : 4/8/2008 1:46:08 AM GMT

Paul Baker

The pipeline is SDIR, Source-Destination-Instruction-Result. The Instruction stage is the fetch for the next instruction (therefore this instruction was fetched 2 clock cycles before the Source fetch). The Full pipeline looks like this:

IdSDER               'first instruction
    IdSDER           'second instruction
        IdSDER       'third instruction

These stages are I= fetch instruction, d=decode instruction, S=fetch source operand, D=fetch destination operand, E=execute instruction, R=write result. Stage d is an internal operation, ie no access to memory is performed. I, S and D are all read operations, so that only leaves 1 stage to make an "effect". So all alterations of a cog's state is performed in the Result stage, whether it's writing to outa or whatever. INA is sampled during Execute, and that value is written to the destination the following clock cycle.

I don't know why you're asking about clock polarity, the system works on the same polarity so it doesn't have any effect on execution.

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Paul Baker
Propeller Applications Engineer

Parallax, Inc.

kuroneko

Thanks, that's all I wanted to know.

Phil Pilgrim (PhiPi)

Paul Baker said...
INA is sampled during Execute, and that value is written to the destination the following clock cycle.

By "destination" here you mean the INA register, right (i.e. not the Destination of the instruction)? This would seem to allow two clocks between "sampling" the pin and reading INA as a source register in the next instruction. That begs the question: Is this another way of saying that a two-stage synchronizer is employed (see illustration)? Although this would have no effect on the timing of ordinary instructions, it could have profound effect on WAITPEQ and WAITPNE (see this thread). If neither of my schematics is accurate, can you suggest one that is?

Thanks,
Phil

kuroneko

Phil Pilgrim (PhiPi) said...
By "destination" here you mean the INA register, right (i.e. not the Destination of the instruction)?

There is no INA register as such.

The Propeller Manual said...
INA is read-only and is not really implemented as a register but rather is just an address that, when accessed as a source item in an expression, reads the Port A I/O pins directly at that moment.

So my interpretation is - backed by my own experiments - Destination of the instruction.

Post Edited (kuroneko) : 5/17/2008 1:18:19 AM GMT

Phil Pilgrim (PhiPi)

The manual would seem to contravene Paul's statement, then. For, if the pins are sampled two clocks ahead of the source being accessed, it has to reside somewhere in the interim, and that somewhere has to be a register. My interpretation of the manual is that INA is not a register in the sense that it can be written to; but still, there has to be some kind of storage involved, if Paul's statement is correct. That's why I always prefer a schematic over a verbal explanation. I guess I'm looking for more of a hardware explanation than a programming explanation. Such would eliminate a lot of ambiguity.

kuroneko said...
So my interpretation is - backed by my own experiments - Destination of the instruction.

But INA can't be the destination of an instruction, since it's read-only.

-Phil

Post Edited (Phil Pilgrim (PhiPi)) : 5/17/2008 2:51:43 AM GMT

Cluso99

Paul's response makes sense, in that the Execute phase of a Waitxx would simply repeat this step until the condition is met. The would actually be read directly from the pins in this cycle and input directly to the compare gates to give an immediate result, or as in the case of a mov xxx,INA the pins would be written back on the next cycle (the Result phase).

Shortly I will be able to release my Data Logger which may shed some light on this (samples every 4 cycles or 50nS at 5MHz xtal). I am hoping to interleave 4 cogs to sample on each clock cycle (12.5nS).

Phil Pilgrim (PhiPi)

Okay, I think I see what's going on. When Paul says "destination" he means the result of MOV dest,INA or ADD dest,INA, for example, is written to dest, which occurs during the R cycle. This would lend credence to the hypothesis that there's no input synchronization going on, except the one-clock sample that occurs during the E cycle. This means that the pins, when read, are gated into the processor two cycles later than other source operands. In that sense, they are treated as an exception, in lieu of reading the source register latched during the S cycle.

I'd still like to see a schematic. It would cut through so much verbiage.

-Phil

Cliff L. Biffle

Or if not a schematic, some formal state machine definitions and timing diagrams. Atmel's AVR datasheets are good examples of how to express all this well.

Harley

Cluso99 said...

Shortly I will be able to release my Data Logger which may shed some light on this (samples every 4 cycles or 50nS at 5MHz xtal). I am hoping to interleave 4 cogs to sample on each clock cycle (12.5nS).

Check out Hanno Sander's ViewPort source for 80 MHz sampling and phasing. I use it, though have only enough cogs for 20 MHz sampling, which works great and totally serves my needs.

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Harley Shanko

Cluso99

Harley,

Do you have a link? All searches seemed to come up with the same newspaper clip.
All,

I released my DataLogger last night. 1 Cog = 50nS (4 clocks)

Latest release samples every clock cycle (12.5nS). Now we can see some instruction timings.

Post Edited (Cluso99) : 5/19/2008 2:13:36 PM GMT

Paul Baker

Sorry for the confusion, Full Description of the pipeline is:
1) fetch next instruction
2) decode instruction
3) fetch source value
4) fetch destination value (this stage is nop for certain instructions (the unary operators))
5) execute instruction
6) write result to destination (this stage is nop when nr option specified)

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Paul Baker
Propeller Applications Engineer

Parallax, Inc.

Post Edited (Paul Baker (Parallax)) : 5/20/2008 10:45:00 PM GMT