I/O cycle timings
![kuroneko](https://forums.parallax.com/uploads/userpics/859/nNPRH0WDKL48I.png)
When writing an output value to e.g. OUTA, when does the output (pin) actually change in terms of instruction cycles (1-4). Also, when reading from INA, which instruction cycle does latch the value available at the input pin? For the latter, it may well be that the inputs are sampled with the system clock (I simply don't know), if so which edge?
TIA
Post Edited (kuroneko) : 4/8/2008 1:46:08 AM GMT
TIA
Post Edited (kuroneko) : 4/8/2008 1:46:08 AM GMT
Comments
These stages are I= fetch instruction, d=decode instruction, S=fetch source operand, D=fetch destination operand, E=execute instruction, R=write result. Stage d is an internal operation, ie no access to memory is performed. I, S and D are all read operations, so that only leaves 1 stage to make an "effect". So all alterations of a cog's state is performed in the Result stage, whether it's writing to outa or whatever. INA is sampled during Execute, and that value is written to the destination the following clock cycle.
I don't know why you're asking about clock polarity, the system works on the same polarity so it doesn't have any effect on execution.
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Paul Baker
Propeller Applications Engineer
Parallax, Inc.
Thanks,
Phil
So my interpretation is - backed by my own experiments - Destination of the instruction.
Post Edited (kuroneko) : 5/17/2008 1:18:19 AM GMT
But INA can't be the destination of an instruction, since it's read-only.
-Phil
Post Edited (Phil Pilgrim (PhiPi)) : 5/17/2008 2:51:43 AM GMT
Shortly I will be able to release my Data Logger which may shed some light on this (samples every 4 cycles or 50nS at 5MHz xtal). I am hoping to interleave 4 cogs to sample on each clock cycle (12.5nS).
I'd still like to see a schematic. It would cut through so much verbiage.
-Phil
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Harley Shanko
Do you have a link? All searches seemed to come up with the same newspaper clip.
All,
I released my DataLogger last night. 1 Cog = 50nS (4 clocks)
Latest release samples every clock cycle (12.5nS). Now we can see some instruction timings.
Post Edited (Cluso99) : 5/19/2008 2:13:36 PM GMT
1) fetch next instruction
2) decode instruction
3) fetch source value
4) fetch destination value (this stage is nop for certain instructions (the unary operators))
5) execute instruction
6) write result to destination (this stage is nop when nr option specified)
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Paul Baker
Propeller Applications Engineer
Parallax, Inc.
Post Edited (Paul Baker (Parallax)) : 5/20/2008 10:45:00 PM GMT