Memory access / pipelining question.

stevenmess2004

This is really a general question about processors that use pipelining. The AVR chips can do 1 instruction/ clock cycle for most instructions. Similarly, the propII will be able to do 1 instruction / clock cycle. This is really nice but how do you fit in the memory accesses? For the AVR chips you need will need 3 for each instruction and 4 for the propII. Does the memory actually run at a higher frequency or is the memory accessed at different parts of the clock cycle (e.g. rising and falling edges of clock)?

I don't need to know I'm just interested. If someone has a link to something it would be good.

Mike Green

Generally, you will get some idea of the timing involved and how memory accesses are processed by reading the datasheets for the processors involved. Often they have timing diagrams that will help. Sometimes the processor internally uses a clock that's a multiple of the system clock. Sometimes the memory is wider than the processor data paths so that successive bytes in an instruction are actually fetched in groups. Sometimes the instruction memory and data memory can be accessed simultaneously so the next instruction is accessed while the data for the current instruction is being accessed. Often several instructions are pipelines so that the different phases of instruction execution are going on simultaneously for adjacent instructions. Look up pipelining on the Wikipedia. Also look up articles and books on the history of computing that discuss early computers that did this like the Cray-1 and the Control Data 6600 and the IBM 360/94.