Shop OBEX P1 Docs P2 Docs Learn Events
Counters and traditional PLLs — Parallax Forums

Counters and traditional PLLs

stevenmess2004stevenmess2004 Posts: 1,102
edited 2008-03-10 15:39 in Propeller 1
I am currently studying PLLs at tafe and have some questions about the timers.

Am I correct that in the PLL modes the output comes straight from the PLL which is linked to bit 31 of PHSA? This means that (ignoring the 160MHz limit) we can get 40MHz*16=640MHz out.

In traditional plls you have a
[noparse][[/noparse]phase comparator]->---[noparse][[/noparse]filter/amp]--->----[noparse][[/noparse]vco]---->-output
.                  |                                                     |
.                  |                                                     |
.                   ---<-----[noparse][[/noparse]divide by N]--------------<---

From the picture that deSilva posted what is in the propeller is (in PLL mode)
[noparse][[/noparse]system clock]------[noparse][[/noparse]?]-------[noparse][[/noparse]phase comparator]-----[noparse][[/noparse]vco]---[noparse][[/noparse]/1 or 2 or 4 or 8 or 16]---output
.                                                   |                          |
.                                                   |                          |
.                                                    ----[noparse][[/noparse]/16]------------



Is this correct and is there an easy way to describe what is in the [noparse][[/noparse]?] block? Does anyone know how fast the PLL responds? It also seems like it would be useful to be able to hook the output of one timer to the input of another (like using one of the logic modes) to help generate more frequencies without glitches. Can this be done?

Edit: forum ate the spaces. lets hope its fixed now...

I have Andre's book on order so if all of the answers are in there than don't worry about a reply if you don't want to smile.gif

These questions are mainly because I have been reading a lot of the old threads that were talking about some of this stuff.

Comments

  • deSilvadeSilva Posts: 2,967
    edited 2008-03-07 11:08
    There is also this fine diagram from my Tuturial smile.gif

    a) Yes you can couple timers by pins - see my example in Mosquito's thread the other day smile.gif

    (Edit: But it will ALWAYS be synched by the system clock!
    Look: The counters do nothing but conditionally(!) add FRQ to PHS each system clock. Period!)

    b) The PLL is rated to work between 4 and 8 Mhz only, giving you 64 to 128 MHz or a fraction of it
    The reason for such constraints is that it's electrical basis is a VCO, which of course has a max voltage... and it does not work very linear at lower voltages

    Post Edited (deSilva) : 3/7/2008 12:31:30 PM GMT
    720 x 480 - 42K
  • Paul BakerPaul Baker Posts: 6,351
    edited 2008-03-07 19:03
    Hi Steven, have you read through AN001 - Propeller Counters? It doesn't go into too much detail on the internals of the PLL, but does show how it's integrated into the Propeller.

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    Paul Baker
    Propeller Applications Engineer

    Parallax, Inc.
  • stevenmess2004stevenmess2004 Posts: 1,102
    edited 2008-03-07 22:01
    Thanks Paul, I had had a look at AN0001 but I somehow missed the PDF before. In figure 7 it shows the clock in going to the VCO. Is this for use in the PLL modes or one of the other modes?
  • deSilvadeSilva Posts: 2,967
    edited 2008-03-07 22:24
    Fig 7 is more a "typical" PLL, but the clock itself is of little significance as used with the phase comparator only.
    I think the VCO will be enabled in mode 1,2,3 only!
  • Paul BakerPaul Baker Posts: 6,351
    edited 2008-03-07 22:39
    deSilva is correct, the PLL is only in modes 1,2 and 3 and bypassed in all other modes.

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    Paul Baker
    Propeller Applications Engineer

    Parallax, Inc.
  • stevenmess2004stevenmess2004 Posts: 1,102
    edited 2008-03-08 05:56
    So, after playing around with some numbers for a while.

    The input clock (80MHz) gets divided down by 2^32/FRQx, but, this only comes out exactly when only a single bit is set (ie it is 2^y where y is an integer).

    This may be a problem as the only value for y that will get in the limits is 28 which will give 5MHz into the PLL and 80MHz out.

    I presume that the PLL averages (filters) the input (bit 31 of PHSx) and therefore has a limited bandwidth. Does anyone know what this is or maybe the period of time over which an average is taken? This will affect what values of FRQx (specifically values that are not powers of 2) can be used without affecting the stability or introducing glitches.
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2008-03-08 07:35
    If jitter is an issue, why not use the Prop's PLL output to synchronize an external VCO-driven PLL whose time constant can be made as long as you want? That way you'd have the programmability of the Prop's PLL with the stability that discrete time denies. (OTOH, you could just use the Prop to program an integrated frequency synthesizer designed for RF use.)

    -Phil
  • stevenmess2004stevenmess2004 Posts: 1,102
    edited 2008-03-08 07:46
    At the moment I'm mainly interested in what the propeller can do by itself. Like I said I'm currently doing a class at tafe where we are studying PLLs and superhet receivers. I guess what I really want to know is if you can make a SDR (transmit and receiver) with just a propeller, resistors, capacitors and inductors. From what I have seen the propeller can easily handle the transmitting but produces a lot of interference. The interference seems to be because of the jitter in the way the PLLs work and I was wondering if there is any way to reduce it.
  • deSilvadeSilva Posts: 2,967
    edited 2008-03-08 09:04
    You are aware that David ("Drone") is persuing these same investigations at the same time!?
  • stevenmess2004stevenmess2004 Posts: 1,102
    edited 2008-03-08 10:44
    deSilva, Sorry, I started out slightly differently and didn't want to steal his thread and it has ended up at the same place.

    Phil, do you know how hard these rf synthesisers are to hook up, where I can look for them and how much they cost?
  • statemachinestatemachine Posts: 24
    edited 2008-03-09 14:04
    · stevenmess2004,I truly believe it would be much simpler to hack an existing radio than try to design a front end and transmitter section.

    Post Edited (statemachine) : 3/9/2008 2:09:34 PM GMT
  • Michael OBannonMichael OBannon Posts: 19
    edited 2008-03-10 15:39
    I've successfully used this frequency synthesizer chip, interfaced to the Prop via i2c:

    http://www.silabs.com/public/documents/tpub_doc/dsheet/Timing/Frequency_Control/en/si570.pdf

    The chip is rather expensive in quantities of one, however. Actually, its rather expensive, period.

    It would be nice to see some schematics for successfully dealing with spurs and phase jitter from the NCO. I'm currently experimenting with using a crystal as a series resonant element connected directly to the output pin of a counter. The problem with this approach is that it severely limits the range of frequency available, and crystals are expensive for VHF. I don't know if overtone crystals will work at all. The approach does allow narrow-band fsk at HF, though.
Sign In or Register to comment.