Help with clock cycles
Mike G
Posts: 2,702
All, I’m working on an assembly serial driver for the Dyanmixel AX-12 servo. The AX-12 has a return delay of 500 uS
Here is my clock set up.
CON
_clkmode = xtal1 + pll16x
_xinfreq = 5_000_000
So that’s 80_000_000 Mhz c/s
Therefore 500uS is 80 X 10^6 /s * 500 X 10^-6s = 40,000 clock cycles.
So my mindset is that I have a lot of time to execute instructions before the AX-12 sends a response packet. But that’s not the case in real life. I can execute 7 commands (7*4=28 clock cycles) and still detect the start bit of the response stream. I add one more op code and no dice. So either the AX-12 is responding right away or I’m missing something related to op codes and clock cycles or my code has a problem. Any ideas?
Mike
Post Edited (Mike G) : 2/22/2008 2:52:41 PM GMT
Here is my clock set up.
CON
_clkmode = xtal1 + pll16x
_xinfreq = 5_000_000
So that’s 80_000_000 Mhz c/s
Therefore 500uS is 80 X 10^6 /s * 500 X 10^-6s = 40,000 clock cycles.
So my mindset is that I have a lot of time to execute instructions before the AX-12 sends a response packet. But that’s not the case in real life. I can execute 7 commands (7*4=28 clock cycles) and still detect the start bit of the response stream. I add one more op code and no dice. So either the AX-12 is responding right away or I’m missing something related to op codes and clock cycles or my code has a problem. Any ideas?
Mike
Post Edited (Mike G) : 2/22/2008 2:52:41 PM GMT
Comments
After some minutes looking through your file, there are two thoughts..
(a) Where is the pull-up? For a halfduplex line you need a - say 1k - to pull the line to idle.
(b) You are XORing the DIRA. This is done most likely in the correct way but it will be much safer to use OR and ANDN for it!