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Possible to sync video PLLs in multiple cogs for VGA driver? (Yes!, well 2 at — Parallax Forums

Possible to sync video PLLs in multiple cogs for VGA driver? (Yes!, well 2 at

RaymanRayman Posts: 14,162
edited 2008-02-13 04:51 in Propeller 1
So, I want run 3 VGA drivers at the same time in order to·do some strange things...· (for instance, 6-bit color by having one cog for each of red,blue,green).· I can syncronize them with waitcnt, but the PLL aren't synced...· Anybody know how to do this?· Or, if it is possible?

This appears to be done in the 1024x768 driver:
' Synchronize all cogs' video circuits so that waitvid's will be pixel-locked
                                                                                              
                        movi    frqa,#(pr / 5) << 2     'set pixel rate (VCO runs at 2x)                     
                        mov     vscl,#1                 'set video shifter to reload on every pixel
                        waitcnt cnt,d8_d4               'wait for sync count, add ~3ms - cogs locked!
                        movi    ctra,#%00001_110        'enable PLLs now - NCOs locked!
                        waitcnt cnt,#0                  'wait ~3ms for PLLs to stabilize - PLLs locked!
                        mov     vscl,#100               'subsequent WAITVIDs will now be pixel-locked!

I've been trying a few things like this:
' Entry                  'First, sync with other vga cogs !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
'
WaitSync                mov     t1,par    'calculate sync cnt address
                        sub     t1,#4
                        rdlong  cnt2sync, t1  'get sync cnt
                        
                        movi    frqa,#afrq'136'(65 / 5) << 2  'set pixel rate (VCO runs at 2x)                     
                        mov     vscl,#1                'set video shifter to reload on every pixel
                        
                        waitcnt cnt2sync,d8_d4        'sync
                        movi    ctra,#%00001_101        'enable PLLs now - NCOs locked!
                        waitcnt cnt2sync,#0                  'wait ~3ms for PLLs to stabilize - PLLs locked!
                        mov     vscl,h1'#100               'subsequent WAITVIDs will now be pixel-locked!


But, haven't figured out how to get it right yet...

Post Edited (Rayman) : 2/12/2008 9:06:22 PM GMT

Comments

  • RaymanRayman Posts: 14,162
    edited 2008-02-11 17:40
    Anybody?
  • RaymanRayman Posts: 14,162
    edited 2008-02-11 17:43
    Here's an example of what I want to do, but·using the XGA driver...

    This code starts 2 syncronized XGA drivers.· Possible uses of strikethrough and underlined text are show.

    I'd really like to get this working for the VGA driver though...
    spin
    spin
    Test_XGA6.spin
    12K
    spin
    spin
    XGA6.spin
    52K
    StrikeUnder.JPG
    1152 x 864 - 128K
  • dfletchdfletch Posts: 165
    edited 2008-02-11 18:13
    Watching this thread with interest. If anyone can shed light I'll include this in the VGA learning driver.

    Rayman: What about doing a synchronized WAITCNT where all cogs wait for the same cnt value before starting? It's completely a guess smile.gif

    Good luck!

    Cheers,

    --fletch
  • RaymanRayman Posts: 14,162
    edited 2008-02-11 18:19
    Yes, I did that, but it's not enough... The PLLs have to be syncronized too...
  • dfletchdfletch Posts: 165
    edited 2008-02-11 18:24
    Hmm yeah you even start ctra right after waitcnt. That would have been my guess too. That'll teach me to post before reading the code smile.gif My bad.
  • cgraceycgracey Posts: 14,133
    edited 2008-02-11 20:47
    The first code snippet in the top message of this thread does what you are wanting to do, though some additional setup code was not shown. The synchronization must be done in stages.

    First, an initial common-value WAITCNT must be executed on all involved cogs. This will sync instruction execution, which can subsequently be used to sync the CTRA's and their PLL's. The instruction sequence following this WAITCNT must be the same on all COGs to ensure synchronization.

    Then, CTRA and FRQA must be configured for PLL function mode %00001·(it is assumed that all PHSA's·were zeroed from reset) and VCFG and VSCL must be configured to reload on every pixel (VSCL=1). This will sync all CTRA's and start the video shifters (which will rev up along with the PLL's).

    Another ~ms will be required to allow the PLL's and the PLL-driven video shifters to synchronize, as well. This can be done with a simple common delay or WAITCNT. Note that the video shifters will be reloading on every pixel clock (which is every PLL clock, since VSCL=1).

    Then, VSCL must be set to a value of, say, 100, to allow the various code branches to occur before all cogs settle into their initial WAITVID's, which will be synchronized.

    Here is the complete VGA 1280x1024 Tile Driver:

    http://obex.parallax.com/objects/176/

    Note that the subtle key to getting the video shifters synchronized was to have them reload on EVERY pixel, keeping them all in a common state. Since the CTRA's were synced, and additional time was allowed for the PLL's to sync, and the video shifters were reloading on every single PLL cycle, AND code execution was synced across all cogs, that final MOV VSCL,#100 set the next WAITVID time marker 100 pixels into the future, allowing all cogs to get into their unique WAITVID's so that they could each play their differentiated roles in the video production. Thereafter, each cog must do WAITVID's to elapse all necessary time chunks to stay in sync with the other cog's. Or, in other words, WAITCNT is no longer the sync mechanism, but WAITVID is.

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔


    Chip Gracey
    Parallax, Inc.

    Post Edited (Chip Gracey (Parallax)) : 2/11/2008 8:54:00 PM GMT
  • RaymanRayman Posts: 14,162
    edited 2008-02-11 21:03
    Thanks Chip! I spent 30 minutes yesterday trying to adapt the XGA sync for a pair of VGA drivers, but couldn't get it going... Hopefully, this new detail will help... I really want to get a 6-bit color mode going... I guess I could do it with 3 XGA's, but that would use up all the cogs and the image size would be tiny...
  • RaymanRayman Posts: 14,162
    edited 2008-02-11 21:12
    Chip:· Any chance you could explain what this does:

    waitcnt cnt,d8_d4               'wait for sync count, add ~3ms - cogs locked!

    I don't get it!·· I would think this either doesn't wait or waits 34 seconds...· What gives?
  • RaymanRayman Posts: 14,162
    edited 2008-02-11 22:22
    Chip: Actually, this was from the 1024x768 driver... It isn't in the OBEX for some reason...

    Anybody know about how "waitcnt cnt,d8_d4" works? Maybe I'll look in "Tricks&Traps"...

    Searched everywhere (even deSilva's Assembly Tutorial!) and still don't see how "waitcnt cnt" is supposed to work...

    Post Edited (Rayman) : 2/11/2008 10:31:56 PM GMT
  • LawsonLawson Posts: 870
    edited 2008-02-12 01:44
    ah! CNT is used as the destination register and CNT is a read only register, thus he's using the "shadow ram" for CNT as extra storage space.

    marty

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    Lunch cures all problems! have you had lunch?
  • RaymanRayman Posts: 14,162
    edited 2008-02-12 01:57
    Thanks!· Searching "shadow ram", I got this:

    http://forums.parallax.com/showthread.php?p=613987

    I think it's too late for me today to get a grip on this though...

    To flame the board a bit...· Here's a little Photoshop test of what a 6-bit image might look like:
    6bitGore.png
    533 x 349 - 35K
  • RaymanRayman Posts: 14,162
    edited 2008-02-12 12:06
    Still don't have it...
    Here's what I have so far:
    Note:· I'm using the long before the regular parameters to pass the cnt to sync to.· I'm printing blue lines with one driver and red lines with the other and hoping to make magenta...· It seems that now the driver PLL are in sync, but offset by 40 ns or so...· So, I'm closer, but not there yet...
    Be sure to uncomment out this line:
    vga.start(@vga_parameters)




    Post Edited (Rayman) : 2/12/2008 7:12:17 PM GMT
    spin
    spin
    VGA6.spin
    24K
    spin
    spin
    HelloWorld_VGA6.spin
    20K
  • RaymanRayman Posts: 14,162
    edited 2008-02-12 19:17
    Got it!
    Just commented out the last step in the sync routine:
    mov     vscl,#500

    And now it works!· (red+blue=magenta)

    PS:· This is also a trick for red-blue 3D in 2-bit color...

    Here's the working files:
    spin
    spin
    VGA6.spin
    24K
    spin
    spin
    HelloWorld_VGA6.spin
    20K
  • dfletchdfletch Posts: 165
    edited 2008-02-12 19:31
    Sweet!

    I'll be adding something similar to the VGA Line Driver in the VGA learning kit soon.

    Still trying to get a basic graphics object working first though, which will also make it simpler to test this!

    Glad you figured it out smile.gif

    Cheers,

    --fletch
  • RaymanRayman Posts: 14,162
    edited 2008-02-12 19:41
    Added a third VGA, but it's not lined up! How can this be? Back to the drawing board...
  • Jasper_MJasper_M Posts: 222
    edited 2008-02-12 21:25
    Try assigning VSCL AFTER the Waitcnt, as the video hardware seems to start counting pulses right when VSCL > 0. so it might be that the internal video counter might be 1 on one cog and 0 on another one...
  • RaymanRayman Posts: 14,162
    edited 2008-02-13 02:23
    I'm starting to think that maybe Chip Gracey is the only one who can do this... Turn out my first two synced VGA's weren't as synced as I thought... Under a microscope, my monitor shows a blue edge with a "real" magenta and a red edge with my dual vga magenta... So, I think they're actually a couple ns off...

    I think I can so proof of concept with XGA drivers anyway, so I think I'll punt on sync'd VGA for now...
  • stevenmess2004stevenmess2004 Posts: 1,102
    edited 2008-02-13 02:27
    Leave it for a day or two and then look at it again. Does wonders smile.gif
  • cgraceycgracey Posts: 14,133
    edited 2008-02-13 04:51
    About sync'ing multiple cogs for video... There is going to be some sub-nanosecond delays between the different cogs, since their output states go through series'd OR gates, from one cog through another, out the to the I/O pins. This will create a slight amount of misalignment, but much less than a pixel's worth. It would help to make sure those three cogs are contiguous, so that the alignment will be tightest.

    I would also recommend using a real CRT, and not an LCD for your driver development, since it will be much more 'analog' and won't suffer from pixel jitter when your timing in't matching up to an LCD's absolute pixel grid. By the time development is over, your driver should work perfectly on most LCDs (some have better PLLs than others, and it seems to have nothing to do with price).

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔


    Chip Gracey
    Parallax, Inc.
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