Shop OBEX P1 Docs P2 Docs Learn Events
Active-Low, what's the point? — Parallax Forums

Active-Low, what's the point?

JedJed Posts: 107
edited 2008-01-31 04:13 in BASIC Stamp
So I'm curious, when would one ever want to use an active low circuit when an active high would work just as well? I mean, an active-low's going to drain battery more correct?

Comments

  • Mike GreenMike Green Posts: 23,101
    edited 2008-01-30 04:35
    Why would active-low drain battery current any more than active-high?

    Some circuits are set up for active low. Party line circuits are often set up using pullups to Vdd and are active-low as a result.
  • FranklinFranklin Posts: 4,747
    edited 2008-01-30 14:46
    Low or high depends on the circuit you are using. On some devices the 'low' is a near ground, this the stamp can do. A high on the other hand means high in relation to the circuit and if the circuit is driven with 5v a high may be MORE than 5v which a stamp by itself cannot do.

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    - Stephen
  • Chris SavageChris Savage Parallax Engineering Posts: 14,406
    edited 2008-01-30 16:36
    This goes much further back as well. Most old-school processors had active-low inputs. Manual entry of code/data was often done by buttons and the lines required pull-ups for their inactive state. In some systems with longer runs of wires to sensors/switches noise immunity is also a consideration. And finally, the BASIC Stamp can translate any active-high input into active-low input and visa-versa using the ~ symbol during the assignment.

    Buttons = ~INL

    This will invert the state of all inputs on P0-P7. So if you’re using active low buttons but would like to see a high as the active input, this single item will accomplish this for you.

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    Chris Savage
    Parallax Tech Support
  • Martin HebelMartin Hebel Posts: 1,239
    edited 2008-01-30 17:43
    Active low inputs are very popular in industry, many sensors go LOW when active - IR detectors and other digital devices. It's easier to pull-high to the desired voltage of the system to which you are interfacing. Outputs are commonly a NPN transistor that is open-collector to be pulled-up to your logic family. When active, the transistor saturates bringing the output low.

    In terms of use, TTL naturally pulls high (though can't always trust), and many processors have internal pull-ups, so to add a switch quick and dirty requires bring the switch low and nothing else.

    In general, I've seen far more active-low inputs in processes than active high.

    -Martin
    Corrected: NPN

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    SelmaWare Solutions - StampPlot GUI for controllers, XBee and Propeller Application Boards

    Southern Illinois University Carbondale, Electronic Systems Technologies

    American Technical Educator's Assoc. Conference·- April, Biloxi, MS. -- PROPELLER WORKSHOP!

    Post Edited (Martin Hebel) : 1/30/2008 8:02:24 PM GMT
  • Tim-MTim-M Posts: 522
    edited 2008-01-30 18:24
    In industry, safety is a major consideration too and this includes noise rejection. Consider a low voltage sensor at the end of a long cable. We know that this cable will be acting somewhat like an antenna picking up and the electrical and RF noise around it... if the sensor is set up to be active-high, then our uC will see this noise voltage on the input and if that voltage becomes high enough, false triggers may be possible. But if the sensor is set up as active-low, no matter what noise happens to be induced, it doesn't provide the ground path that is needed and is much better in a noise rejection sense. Granted there are many techniques to help avoid false triggers in an active-high situation, but like Martin said, active-low is much more common in industrial gear.

    Tim
  • Tracy AllenTracy Allen Posts: 6,666
    edited 2008-01-30 22:49
    Historically, back to the dawn of transistors anyway, it has always been easier to make good NPN transistors than good PNP. Same for N-channel fets vs P-channel. They are faster and conduct better, due to the mobility of electrons in the N type semiconducter, versus the mobiity of the "holes" that make a P type. When making a transistor switch for an output stage of a logic chip or to drive a power load, it becomes more attractive to have an NPN transistor sinking current to ground instead of a PNP sourcing current from the power supply. To a certain extent this is still true. In designing a chip like the one in the BASIC Stamp, special care had to be given to the geometry of the P-channel source drivers in comparison to the N-channel sink drivers, to make sure the chip outputs could operate in pretty much a symmetrical manner.

    You asked, "I mean, an active-low's going to drain battery more correct?". No, not true. It is the same current, whether it comes from the battery, to the switch to the load to ground, versus from the battery, to the load to the switch to ground.

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    Tracy Allen
    www.emesystems.com
  • Beau SchwabeBeau Schwabe Posts: 6,568
    edited 2008-01-31 04:13
    Tracy,

    Agreed.... The N-type transistor be it an NPN, or NMOS, etc. is easier because as you say "the mobility of electrons in the N type semiconductor". With a P-type transistor a separate WELL needs to be created to form the transistor. This "WELL" has a higher resistance than the N-type counter part. To compensate against the higher resistance, P-type transistors are almost always made larger by a factor ranging from 2 to 4 times their N-type complementary counter part. This increase in size contributes to a larger capacitance, and can lead to a slower transistor.

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    Beau Schwabe

    IC Layout Engineer
    Parallax, Inc.
    963 x 505 - 98K
Sign In or Register to comment.