Reading the output state of a smartpin

Comments

• Rayman Posts: 13,901

  2020-12-22 12:35

  The source selector would work
• ManAtWork Posts: 2,080

  2020-12-22 12:56

  But it requires an extra pin? If not, how can I read the pin state? Not via INA/INB or TESTP because theese show the event flag "period completed" instead of the actual pin state, don't they.
  

  Normally, an I/O pin's output enable is controlled by its DIR bit and its output state is controlled by its OUT bit, while the IN bit returns the pin's read state. In smart pin modes, the DIR bit is used as an active-low reset signal to the smart pin circuitry, while the output enable state is controlled by a configuration bit. In some modes, the smart pin takes over driving the output state, in which case the OUT bit gets ignored. The IN bit serves as a flag to indicate to the cog(s) that the smart pin has completed some function or an event has occurred, and acknowledgment is perhaps needed

  A counter, updating at each base period, counts from the frame period down to one, then from one back up to the frame period. Then, Y[15:0] is captured, IN is raised, and the process repeats.
• Rayman Posts: 13,901

  2020-12-22 13:41

  Yes, you need another pin.
  But that one pin could cycle through its six neighbors
• Rayman Posts: 13,901

  2020-12-22 13:42

  It is kind of unfortunate that a smartpin is blind to itself
• Rayman Posts: 13,901

  2020-12-22 13:45

  In my mixed signal scope example, there are six digital channels shown. Three are in NCO mode and three are spying on these NCO neighbors
• ManAtWork Posts: 2,080

  2020-12-22 14:02

  Ok, I see. Then I have bad luck because I've already finished layout and board assembly. The four PWM pins for one motor have consecutive numbers so I can't reach them all with only one extra pin.
  
  Then I have to pre-calculate the blanking windows and run a software counter to track the PWM state. Shouldn't be too complicated although I have hoped to get rid of that cycle-counting with the P2 smart pins.
  
  Thanks, Rayman.
• Rayman Posts: 13,901

  2020-12-23 02:04

  I saw mention of interrupts in your other thread...
  I'm not exactly sure what would happen if you set interrupt on state change of a pin that is in smartpin mode...
  
  I'd guess it wouldn't let you track the actual state of the pin, but hard to say...
• ManAtWork Posts: 2,080

  2020-12-23 10:01

  Yes, I remember somebody has drawn a very big and detailed schematic of the smartpin logic with all the muxes and signal routings. But as often, I can't find it. It's not in the "Smart Pin Supplementary Documentation" by Jon Titus. With that schematic it should be possible to find out if there's a signal path to readback the pin state or not.
  
  But anyway, it's also possible to predict the PWM state change with a simple counter. There are 32 ADC samples per PWM frame. For demodulation of the AC signal I have 3 possibilities based on the compare result of the sample number (n) and the PWM value (v=y<<8) reduced to 5 bits:
  a) sample is before state change (n-v < 0): add to bin0, c0++
  b) sample is in the blanking window (0<=c-v<3): ignore
  c) sample is after blanking window (n-v>=3): add to bin1, c1++
  The final result is (bin0/c0) - (bin1/c1) with c0 = number of samples in bin0 and c1 = samples in bin1. That only takes several assembler instructions, probably even less than reading the pin state and compare to the last state.
• ManAtWork Posts: 2,080

  2020-12-23 10:37

  I've found the "Smartpin diagram" thread:
  http://forums.parallax.com/discussion/171420/smartpin-diagram-now-with-p-p-bit-mode-table/p1
  But it's not the diagram I meant in the last post, there was an even bigger and more detailed one somewhere.
  
  Chip, can you hear me?
  
  We need a P2 data sheet! A real one with ALL the information.
  
• Alexander (Sandy) Hapgood Posts: 360

  2020-12-23 19:24 edited 2020-12-23 19:25

  ManAtWork wrote: »

  Chip, can you hear me?
  
  We need a P2 data sheet! A real one with ALL the information.
  

  
  It's my opinion that the last person you would want to write the data sheet is Chip. Most of the what he knows about the P2 is obvious to him so he would be unlikely to relay information in a way that most people would understand. Just look at most of his demonstrations.
• evanh Posts: 15,192

  2020-12-24 07:27

  ManAtWork wrote: »

  I've found the "Smartpin diagram" thread:
  http://forums.parallax.com/discussion/171420/smartpin-diagram-now-with-p-p-bit-mode-table/p1
  But it's not the diagram I meant in the last post, there was an even bigger and more detailed one somewhere.

  
  I have my guessed logicsim diagrams at end of that same link - http://forums.parallax.com/discussion/comment/1495168/#Comment_1495168
  
  There is also Chip's block diagram he compiled direct from his schematics of the I/O pad ring - https://forums.parallax.com/discussion/comment/1494131/#Comment_1494131
  
  
• evanh Posts: 15,192

  2020-12-24 07:35 edited 2020-12-24 07:39

  ManAtWork wrote: »

  ... However, this doesn't work (directly) because for smart pins the IN value reflects the event bit and not the pin state. Is there a possibility to bypass this without wasting an extra pin (and use the -3..+3 source selector)?

  No, when a smartpin mode is selected, with M > 0, then IN always shows the smartpin event state. You can only then use a nearby pin input to observe the logic level of that physical pin.
  
  PS: This is indicated in Rayman's block diagram with the M == 0 dotted line inside the smartpin block.
  PPS: Maybe the dotted line should have an arrow head added to it.
  
  
• ManAtWork Posts: 2,080

  2020-12-24 10:21

  Ok, I see. Thanks for the clarification.
  
  Then I have to do it with the counter and comperator method. I'll try that.