Random/LFSR on P2

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  • evanhevanh Posts: 10,083
    edited 2020-10-27 - 01:21:05
    All good in Silo New Zealand. :)
  • Since I couldn't wait for the new AMD 5950X CPUs (check the PassMark results) to become available, I went ahead and replaced the MB, and upgraded both the CPUs to Xeon E5-2697 V2 in the process. It cost about $400 US total for the MB and CPUs... that would have been over almost $1000 about a year ago, and about $4000 a year and half ago.
    Hard to beat second hand prices. And that's quad channel too. Likely a decent advantage.

    Yeah, the new Zen3 performance sure feels tempting to me. Sadly, supposedly due to too many models of AM4 socket CPUs overflowing the BIOS size, it looks like Ryzen 5k models won't drop into my B350 mobo. So I'm unlikely to make the move. The existing 1700X is fine of course.

  • evanh wrote: »
    All good in Silo New Zealand. :)
    We had a community case recently, one port worker tested positive after spending time on a docked container ship. It puzzled me that a ship at sea for months in this area of the world could be an infection vector. Turns out eight fresh crew also jumped on board about the same time. These fresh crew had basically been exempted from the full 14 day quarantine period.

    The ship is currently held up offshore at Sunshine Coast, Australia, and two crew have been flown to a hospital there.
  • evanh wrote: »
    evanh wrote: »
    All good in Silo New Zealand. :)
    We had a community case recently, one port worker tested positive after spending time on a docked container ship. It puzzled me that a ship at sea for months in this area of the world could be an infection vector. Turns out eight fresh crew also jumped on board about the same time. These fresh crew had basically been exempted from the full 14 day quarantine period.

    The ship is currently held up offshore at Sunshine Coast, Australia, and two crew have been flown to a hospital there.

    Exemptions make a mockery out of the lockdowns.
    During the big Victoria lockdown workers were granted exemptions to go to Sydney for work almost without any restrictions - they had to return to the designated address to sleep! Basically no other restrictions, no quarantine. I think they had to have a clear COVID test before leaving Victoria - but they could already be infected!
  • evanhevanh Posts: 10,083
    edited 2020-10-30 - 07:57:20
    Cluso99 wrote: »
    Exemptions make a mockery out of the lockdowns.
    Yep. My sister, lives in Brisbane, was getting pissy for a while, early on, because she knew others were getting "self isolation" passes to travel into NZ and camp pretty much anywhere they chose in the North Island at least, but she'd been refused because she wanted to cross the Cook Straight. That all stopped when the Auckland outbreak happened. It became very clear the exemptions were too risky.

    Apparently, diplomats are still exempt though.

  • Yes, please keep on topic.
  • Okay, will do. I hope all the x86 CPU talk isn't off limits at least?
  • evanh wrote: »
    Okay, will do. I hope all the x86 CPU talk isn't off limits at least?

    No, that's fine :)
  • evanh wrote: »
    ... And that's quad channel too. Likely a decent advantage.
    Hard to tell with my work-loads, as I was down to three channels after the repair/upgrade when I moved from 64GB to 32GB of faster RAM I had laying around and found that two sticks were bad. Maybe a 3% improvement under 48 thread load once I replaced those two. That brings me to about the 1.5x improvement expected from moving from V0 to V2 processors with 50% more cores at a 10% reduction in clocks (now 3.0GHz all-core, vs. 3.3GHz before).

    What I find interesting is BigCrush scaling with Intel HT... each HT core equals about 0.5 physical cores. That is to say, about 1.5x, which is much higher than scaling in many benchmarks that focus on HT performance.
  • Hard to tell with my work-loads ...
    True. I only really noticed poor scaling when I was running Tony's paired 16-bit distribution tests. Those needed 4 GB of accumulators per task. When running multiple tasks, up to seven fitted, the performance of the individual task definitely took a hit. As much as half the speed. And I suspect even the single task run was likely nerf'd waiting on the DRAM. L2 and L3 caching weren't much help there I don't think.

  • I was going to avoid the expense of bringing that server back up to 64GB of fast RAM (for those freq, and similar jobs) and save the money for a 5950X build (or maybe a 5900X, if I want to also do a Threadripper build down the road).

    Congrats on 10,000 posts... I think I was (only) way over 8000 on XVBT (XtremeVisualBasicTalk) as a mod (before it finally went belly-up).
  • And someone famous once said 640KB will be more than enough!

    Congrats for reaching the 10K milestone evan.
  • Wow, I never thought I was posting that much. I'll blame all my second guessing posts.

  • xoroshironotxoroshironot Posts: 272
    edited 2020-11-04 - 00:39:51
    I just noticed the 1st place world-record holder for 'Cinebench R15 Extreme' is selling his/her TR 3990X CPU on eBay (at a comparatively reasonable price).
    Must remain calm and resist temptation in order to hold out for DDR5 based next-gen TR.
    However, I did some calculations and determined that I could perform nearly 1000 TestU01 BigCrush runs/day, and all 64-bit rotations of PractRand out to at least 4TB within a week.
    It only takes about 1000 to 4000 BigCrush runs to reasonably demonstrate that many so-called 'good quality' PRNGs (that pass PractRand at 32TB) are not statistically random (or, at least, to derive a starting point for a focused statistical analysis).
  • Hmm, that's a lot of money to be selling off cheap so soon.

  • Wow, the Zen3's are already on the shelf here. Presume they went up on Friday our time.

    Prices are up again, that'll be to slow initail demand I presume. They're definitely giving a price advantage to the 6 and 12 core parts, so there must be quite a lot of production defects.

  • xoroshironotxoroshironot Posts: 272
    edited 2020-11-08 - 15:49:50
    I don't think the defect-free rate of ~93.5% would have changed from Zen 2, since it is the same TSMC process.
    However, binning to get enough higher-speed stock for 5900X and, especially 5950X (which must be defect-free), must be a chore. That might take away from 5800X supply, thus the higher cost.
    Also, perhaps they are cherry-picking chiplets that are both defect-free and high-binned to reserve for a future product release... maybe not, since many factors are at play here, it is hard to predict.
  • Reading some of the reviews it's becoming clear the Zen3 cores are fast! In some tests they're up to double the speed of the Zen2 core. Fast enough to be substantially memory speed limited now. Faster DIMMs makes them all go a lot faster. Even the 5600X.

    I guess one reason may be something like AVX2 getting enabled, not that I know for sure. Zen1 and Zen2 parts I've noticed are flagged as not supporting AVX2 in the Linux kernel even though they do.

  • The recent notable news seems to be that (perhaps) interleaving plays about an 8% performance improvement role when four sticks of RAM are used instead of two sticks. Not like actual quad-channel, but respectable. Oddly, RAM low-latency seems to be more important than speed in many benchmarks, as 3200 CL14 often outperforms faster RAM, but this will be moot as manufacturers rush to release affordable combined low-latency high-speed RAM. 3800/3866 CL14 might become popular (since actual support for 4000 is spotty, but will improve some with new AGESA soon). The ability to overclock Zen 3 to good effect is just icing on the cake, but better have a good motherboard VRM and CPU cooling solution (especially for 5950X). I'm hyped... need to wait a few months for price/availability to shake out.
  • evanhevanh Posts: 10,083
    edited 2020-11-22 - 00:45:44
    I wonder a little how Apple have designed the M1 high-performance core. They've put a lot of execution units in there, to say the least! Each high-performance core features 192 kB of L1 instruction cache, 128 kB of L1 data cache, 8-wide instruction decode, and maybe 16 execution units.

    To make that work together effectively, it would need many data paths between all those execution units and the L1 data cache. Normally that would be many SRAM ports, which costs a lot of transistors ... and bigger RAM blocks also negatively impact latency. 128 kB is bigger than anyone else. Would be L2 territory normally.

    I wonder if maybe Apple have done something like the prop2 with its hubRAM crosspoint switch. Or maybe just separate smaller L1 cache blocks grouped with select execution units.

  • xoroshironotxoroshironot Posts: 272
    edited 2020-11-23 - 22:17:23
    I think M1 is just Apple's 'good enough' transition solution... I expect wonders from next-gen.
    Granted M1 is already on 5nm and has 16 billion transistors, but I'm sure they will figure out some way to move it forward.

    On the AMD front, PBO2 (coming soon) for 5000X CPUs employs opportunistic under/over-volting to facilitate optimal boosting... sweet, as the best will only get better, at no extra cost.

    Edit: I forgot the link: Here
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