Reciprocal Counter Demo

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Comments

  • evanh wrote: »
    ...
    ... You would need a very fast specialized oscilloscope to capture cycle-to-cycle jitter decently. ...
    Note the 20 GS/s at the top. It's a speciality of that scope. I've never used the feature till working the prop2 though.

    EDIT: If you scroll up a little before the linked post, I described how it does that.
    Sorry, Evan. My mistake.

    Kind regards, Samuel Lourenço
  • When I purchased the scope, it was the bottom-end range of Yokogawa's tools. DL-1640 model.

    I really really wanted a 4-channel deep memory scope I could setup inside machinery cabinets, but such tools were so expensive back then. Well before Rigol appeared on the scene. I had put up with a Tektronix for a few years but the lack of deep memory made it near useless for me.

    "Those who think we are powerless to do anything about the greenhouse effect forget about the 'White House effect,'" - George H.W. Bush, 1988.
  • jmgjmg Posts: 14,175
    samuell wrote: »
    But how does that translates to jitter? And how one can infer that a source is more jittery than the other, especially when direct measurements prove otherwise (at least concerning cycle-to-cycle jitter)?

    Jitter has many forms, and meanings. It can also mean variance or uncertainty in measurements.
    There is cycle to cycle to jitter that a Scope shows, and the P2 here is a gated counter, that on average lets thru ~12.5 or ~12.99 sysclk edges per gate, but over 100002 gates.
    So that's a longer average.
    On an ideal gated counter, over the 100002 cycles of 10MHz in, that should always give an answer just as stable as the MHz value.
    This number shows how many sysclks actually were gated (seen by P2), over that 10.0002ms window.

    Here, the results show that does not happen. Something is different between the sources. Broadly, the first test varies in the 4th digit, whilst the 2nd one is better, varying in the 5th digit.

    There is a larger variance in gated totals, than expected, and it is different for your 2 sources.
    It may be jitter/variance in duty cycle itself, as notice the captured duty is quite different (not 50.0% in both cases), or it may be the sampling aperture jitter of the FF.
    A 10MHz signal is tough here, but someone might want to use P2 to capture PWM from a SMPS, and 500k~2MHz is common there.
    Adding a Flipflop to force duty to always 50% would be one useful test..


    There will be some fractional ns window, where the pin-check is not cleanly digital.
    Thus my suggestion to clock P2 from a more precise but not locked clock as another test here.
    Note a P2 with a VCTCXO and a trimpot, would make this type of 'almost sync' testing easier to setup.


  • jmgjmg Posts: 14,175
    evanh wrote: »
    Okay, nope, not even close. Attached is a bunch of consecutive densities (states) as reported by Chip's frequency counter program. Doing what JMG did gives about 180 ppm.

    And I think I know why. In the attach screenshot I've increased the interval of full range view to see the jitter narrow again. It's about 1/10th the amount of jitter every 3.9 4.0 us. So that means, in this particular case, the crystal oscillator is stable but the PLL instability is causing very short oscillations back and forth across the ideal.

    The absolute jitter of about 110 ns then fades wrt the long average (10 ms) of the frequency counter.

    Not all jitter types will act that way though. And indeed 110ns / 10ms only equals 11 ppm so the counter is picking up something more.

    Wow, what is the test setup there exactly ? - What PLL settings ?
    wait, I now see a later post....
    evanh wrote: »
    Don't worry, I am abusing the PLL to get that result, pushing it outside its spec and found a particularly bad spot.
    PS: The setting is 20.5 MHz sys-clock with XDIVP = 1. Normally, XDIVP should be something like 4 when this low. This way the VCO in the PLL will be operating 4x faster.
    Ah, yes the PLL will be seriously current starved to get so low, and so you would expect visible modulation effects.
    if you get a final 20.5MHz that suggests a PFD of 500kHz, so that's lower than the ~ /4 modulation you see here ( ~ 5MHz of FM ?)
    Wonder where that 5MHz comes from ?
  • evanhevanh Posts: 8,610
    edited 2019-12-10 - 19:41:12
    It's same software and same settings from last time you commented in the other topic. The software tries to produce a 1 MHz square wave using smartpin mode NCO_FREQUENCY with Y=$8000_0000 and X with closest match rounded down.

    The "modulation" looks to be 4.0 μs period (250 kHz), or 1/80 of crystal. EDIT: And this could be the half wave I guess.

    "Those who think we are powerless to do anything about the greenhouse effect forget about the 'White House effect,'" - George H.W. Bush, 1988.
  • jmgjmg Posts: 14,175
    samuell wrote: »
    Plus, can I extract a 10MHz clock generated by the P2, given that it is derived from the PLL, in the same conditions that it is being used by Chip's program?
    That's a good idea.
    Code could set up any other pin in Chip's code to output a signal, but 10MHz and 50% is not going to be easy.
    The 250MHz sysclk he chose here, could give 12 cycles hi and 13 cycles low for 10.00MHz (/25) in a pwm mode.

    Hooking that test point to Fin, I'd expect to give 1200000 gated result every time (48.000%), as it is a sync clock.
  • jmgjmg Posts: 14,175
    evanh wrote: »
    The software tries to produce a 1 MHz square wave using smartpin mode NCO_FREQUENCY with Y=$8000_0000 and X with closest match rounded down.

    The "modulation" looks to be 4.0 μs period (250 kHz), or 1/80 of crystal. EDIT: And this could be the half wave I guess.
    Ah, thanks, I skipped over the time base, and thought that was still 10MHz.
    Asking for 1MHz from 20.5MHz is not going to give a great test case, as it needs to /20/21/20/21 alternating which is 48.78ns of edge wobble just in the NCO effect.

    A PLL PFD of 500KHz could be expected to give a 'go up' alternating with 'go down' correction at 500KHz and that will modulate at 250kHz

  • evanhevanh Posts: 8,610
    edited 2019-12-10 - 20:44:48
    Y=$8000_0000 The square wave is constant regular. It's just a little faster than 1 MHz is all.
    "Those who think we are powerless to do anything about the greenhouse effect forget about the 'White House effect,'" - George H.W. Bush, 1988.
  • I've brought up the FFT on the scope. Not sure of it's effectiveness. Here's both a clean 80 MHz sys-clock reference and the dirty 20.5 MHz sys-clock.
    80.0MHz_FFT.PNG
    20.5MHz_FFT.PNG
    640 x 480 - 12K
    640 x 480 - 14K
    "Those who think we are powerless to do anything about the greenhouse effect forget about the 'White House effect,'" - George H.W. Bush, 1988.
  • jmgjmg Posts: 14,175
    edited 2019-12-10 - 22:27:33
    evanh wrote: »
    Y=$8000_0000 The square wave is constant regular. It's just a little faster than 1 MHz is all.
    Ah yes, the NCO distracted me.
    Configured that way, you have SysCLK/2/N, and N=10 gives a predicted time of 3.90243us for 4 cycles, which is what your scope shows as the mean, now I look closely at the scales.

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