HDMI added to Prop2

17810121321

Comments

  • TonyB_TonyB_ Posts: 1,414
    edited 2018-10-25 - 13:04:08
    Sequence below generated using first 256 XORO32 outputs when seed = 1. Byte input to TMDS encoder is low byte of XORO32 output, i.e. PRN[7:0] and PRN[31:8] are ignored.

    For xoroshiro32++ [14,2,7,5] as in first silicon and v32i image

    8b = 8-bit input
    10b = 10-bit output
    dispi = disparity input from previous stage
    dispo = disparity output to next stage
    disparity = number of '1' bits - number of '0' bits for 8-bit value
    #8b,10b,dispi,dispo
    21,11F, 0,+2
    9A,223,+2, 0
    87,17D, 0,+4
    AA,233,+4,+4
    40,1C0,+4, 0
    87,17D, 0,+4
    AC,231,+4,+2
    C1,340,+2,-2
    58,337,-2,+2
    3D,041,+2,-4
    E3,2F4,-4,-2
    20,31F,-2,+2
    E9,00D,+2,-2
    B8,23D,-2, 0
    1C,1F4, 0,+2
    9A,223,+2, 0
    7F,280, 0,-6
    AC,0CE,-6,-6
    42,13E,-6,-4
    93,171,-4,-4
    E6,2F7,-4,+2
    6D,28E,+2,+2
    31,310,+2,-2
    7D,27E,-2,+2
    F9,202,+2,-4
    43,33E,-4, 0
    88,178, 0, 0
    D3,2E4, 0, 0
    D8,21D, 0, 0
    C6,217, 0, 0
    FB,2FC, 0,+4
    F7,007,+4, 0
    D0,1B0, 0,-2
    17,3F2,-2,+2
    F8,002,+2,-6
    19,1F7,-6, 0
    6B,28C, 0,-2
    C2,1BE,-2,+2
    60,120,+2,-4
    4E,26F,-4, 0
    3B,2BC, 0,+2
    19,308,+2,-2
    73,07B,-2, 0
    32,1EE, 0,+4
    06,102,+4,-2
    6D,28E,-2,-2
    BF,03F,-2, 0
    D0,1B0, 0,-2
    95,173,-2, 0
    6D,28E, 0, 0
    30,110, 0,-6
    39,117,-6,-6
    52,1CE,-6,-4
    2E,24F,-4,-2
    9A,0DC,-2,-2
    F1,2FA,-2,+2
    11,10F,+2,+2
    E3,00B,+2,-2
    30,3EF,-2,+6
    1F,2A0,+6,+2
    BF,2C0,+2,-2
    8D,17B,-2,+2
    AF,230,+2,-2
    62,1DE,-2,+2
    A4,19C,+2,+2
    46,1C2,+2, 0
    C1,1BF, 0,+6
    53,131,+6,+4
    06,102,+4,-2
    38,1E8,-2,-2
    5F,09F,-2, 0
    B5,2C6, 0, 0
    26,1E2, 0, 0
    99,177, 0,+4
    9A,223,+4,+2
    25,31C,+2,+2
    45,1C3,+2,+2
    91,370,+2,+2
    B1,390,+2, 0
    E5,2F6, 0,+4
    34,313,+4,+4
    9D,021,+4,-2
    3B,2BC,-2, 0
    F9,202, 0,-6
    9B,2DC,-6,-4
    B6,2C7,-4,-2
    94,373,-2,+2
    62,321,+2, 0
    8D,17B, 0,+4
    4E,090,+4,-2
    2F,04F,-2,-2
    34,1EC,-2, 0
    AD,2CE, 0,+2
    D2,21B,+2,+2
    C0,140,+2,-4
    D2,21B,-4,-4
    38,1E8,-4,-4
    76,287,-4,-4
    90,38F,-4, 0
    50,130, 0,-4
    1F,05F,-4,-2
    23,1E1,-2,-2
    48,3C7,-2,+2
    35,113,+2, 0
    C6,217, 0, 0
    71,12F, 0,+2
    0B,306,+2, 0
    F3,204, 0,-6
    DF,01F,-6,-6
    10,1F0,-6,-6
    04,1FC,-6,-2
    55,133,-2,-2
    C4,1BC,-2, 0
    60,120, 0,-6
    B9,03D,-6,-6
    38,1E8,-6,-6
    97,2D8,-6,-6
    56,267,-6,-4
    3C,0BE,-4,-2
    B1,16F,-2,+2
    63,121,+2,-2
    E4,0F6,-2, 0
    EE,20F, 0, 0
    9E,2DF, 0,+6
    58,1C8,+6,+4
    06,102,+4,-2
    B4,239,-2,-2
    9D,2DE,-2,+2
    40,1C0,+2,-2
    96,227,-2,-2
    FC,0FE,-2,+2
    F6,207,+2, 0
    4F,290, 0,-4
    72,27B,-4, 0
    01,1FF, 0,+8
    87,382,+8,+6
    B0,190,+6,+2
    65,123,+2, 0
    1D,10B, 0,-2
    DF,01F,-2,-2
    33,3EE,-2,+4
    38,1E8,+4,+4
    87,382,+4,+2
    30,110,+2,-4
    84,17C,-4,-2
    BC,03E,-2,-2
    16,1F2,-2, 0
    C8,1B8, 0, 0
    4A,1C6, 0, 0
    B1,16F, 0,+4
    FC,201,+4,-2
    76,287,-2,-2
    A1,19F,-2,+2
    FB,003,+2,-4
    F8,2FD,-4,+2
    1F,2A0,+2,-2
    FF,0FF,-2,+4
    2C,1E4,+4,+4
    7F,280,+4,-2
    BB,23C,-2,-2
    E5,2F6,-2,+2
    2B,119,+2, 0
    0F,105, 0,-4
    05,3FC,-4,+2
    B5,2C6,+2,+2
    E6,008,+2,-6
    80,37F,-6,+2
    D5,019,+2,-2
    F4,2F9,-2,+2
    68,1D8,+2,+2
    85,183,+2, 0
    E8,20D, 0,-2
    23,1E1,-2,-2
    72,27B,-2,+2
    84,383,+2,+2
    91,370,+2,+2
    1E,0A0,+2,-4
    42,13E,-4,-2
    31,1EF,-2,+4
    0B,306,+4,+2
    B0,190,+2,-2
    18,3F7,-2,+6
    FE,000,+6,-4
    84,17C,-4,-2
    CA,0EC,-2,-2
    F4,2F9,-2,+2
    1E,0A0,+2,-4
    02,1FE,-4,+2
    82,381,+2, 0
    09,107, 0,-2
    10,1F0,-2,-2
    44,13C,-2,-2
    B7,0C7,-2,-2
    43,33E,-2,+2
    7F,280,+2,-4
    90,38F,-4, 0
    24,11C, 0,-2
    D8,21D,-2,-2
    D0,34F,-2,+2
    9E,020,+2,-6
    3F,0BF,-6,-2
    36,247,-2,-2
    CC,0EE,-2, 0
    46,1C2, 0,-2
    2E,24F,-2, 0
    A4,19C, 0, 0
    88,178, 0, 0
    A4,19C, 0, 0
    C0,140, 0,-6
    1D,3F4,-6,-2
    CA,0EC,-2,-2
    2B,3E6,-2,+2
    B5,2C6,+2,+2
    FB,003,+2,-4
    35,3EC,-4, 0
    B0,190, 0,-4
    30,3EF,-4,+4
    2A,319,+4,+4
    18,108,+4,-2
    9A,0DC,-2,-2
    DA,2E3,-2, 0
    3A,243, 0,-2
    6F,08F,-2,-2
    F3,0FB,-2,+2
    08,307,+2,+2
    9F,220,+2,-4
    F9,0FD,-4, 0
    5B,29C, 0, 0
    18,108, 0,-6
    37,2B8,-6,-6
    C3,3BE,-6, 0
    AB,2CC, 0, 0
    F8,2FD, 0,+6
    62,321,+6,+4
    BA,2C3,+4,+4
    98,188,+4, 0
    60,120, 0,-6
    C1,1BF,-6, 0
    FF,200, 0,-8
    D4,0E6,-8,-8
    3C,0BE,-8,-6
    5A,263,-6,-6
    F7,2F8,-6,-4
    B6,2C7,-4,-2
    B3,03B,-2,-2
    2A,1E6,-2, 0
    F7,2F8, 0,+2
    B8,0C2,+2,-2
    56,267,-2, 0
    87,17D, 0,+4
    67,288,+4, 0
    5B,29C, 0, 0
    CC,211, 0,-4
    A6,237,-4,-2
    3C,0BE,-2, 0
    61,1DF, 0,+6
    
  • TonyB_TonyB_ Posts: 1,414
    edited 2018-10-25 - 13:03:33
    Random sequence above changed to use xoroshiro32++ [14,2,7,5] instead of new [13,5,10,9].
  • Doesn't disparity refer to the 10-bit value?
  • TonyB_TonyB_ Posts: 1,414
    edited 2018-10-25 - 13:33:57
    Rayman wrote: »
    Doesn't disparity refer to the 10-bit value?

    No, disparity applies only to 8-bit input during first stage of encoding and low 8 bits of provisional output during second stage.
  • cgraceycgracey Posts: 12,440
    edited 2018-10-25 - 15:26:38
    TonyB_, Thank you for posting that.

    Both the FPGA and the software versions check out okay with your random data.

    Now I'll see if I can stream out a software-generated 640x480 HDMI signal from the P2 running at 250MHz. I need to get some sleep, first.

    Here's my HDMI test setup. I got a little breakout board on Amazon with screw terminals:


    HDMI_setup.jpg
    1235 x 1107 - 207K
  • Wait, that's a P2D2........Wha??? <Scratches Head>
  • I think Chip started with an unpopulated P2D2 board. Hasn't gone too far on completing it.

  • I was thinking that HDMI could only be done with the new changes chip was making in the FPGA, but was out of reach for P2-SiO2.
  • ke4pjw,
    My understanding is that he's producing the data with the FPGA (too slow to actually work with a TV), saving it and then playing it back on the real chip at 250Mhz via the streamer.
  • Roy Eltham wrote: »
    ke4pjw,
    My understanding is that he's producing the data with the FPGA (too slow to actually work with a TV), saving it and then playing it back on the real chip at 250Mhz via the streamer.

    Current plan is to generate HDMI output in software, write it to hub RAM, then stream it out at 250MHz, all on the P2.
  • Yes, when we get real chips. Until then, testing the HDMI code happens on the FPGA, at a slow rate.

    That captured bitstream goes to a current rev A P2 for testing on a TV.

  • I'm synthesizing the data with a bit of software on the P2 silicon, laying it into memory, then streaming it out at 250MHz. I've confirmed that the software algorithm is the same as the one in the fpga, which is the same that comports with the data that TonyB_ posted. Should be able to try it tonight.
  • jmgjmg Posts: 14,244
    edited 2018-10-25 - 23:00:07
    cgracey wrote: »
    Here's my HDMI test setup. I got a little breakout board on Amazon with screw terminals:
    Does that have resistors for the 10mA HDMI current drive ?

  • jmg wrote: »
    cgracey wrote: »
    Here's my HDMI test setup. I got a little breakout board on Amazon with screw terminals:
    Does that have resistors for the 10mA HDMI current drive ?

    Just straight connections. Do you think we need resistors at 250 megahertz?
  • cgracey wrote: »
    jmg wrote: »
    cgracey wrote: »
    Here's my HDMI test setup. I got a little breakout board on Amazon with screw terminals:
    Does that have resistors for the 10mA HDMI current drive ?

    Just straight connections. Do you think we need resistors at 250 megahertz?

    Are the outputs digital? I think you'll need series resistors, 100 ohm minimum. HDMI receivers have 50 ohm pull-ups to 3.3V.
  • jmgjmg Posts: 14,244
    cgracey wrote: »
    jmg wrote: »
    cgracey wrote: »
    Here's my HDMI test setup. I got a little breakout board on Amazon with screw terminals:
    Does that have resistors for the 10mA HDMI current drive ?

    Just straight connections. Do you think we need resistors at 250 megahertz?

    Yes, I would start with a 'correct' HDMI drive, which is 10mA (500mV into far end's 50 Ohms) & if that works, then you can see if it tolerates a full 3V3 swing.
    3v3 is likely to be outside the common mode range of any receiver, not to mention you are asking P2 to sink up to ~ 66mA if driving that 50 Ohms direct, and you are above 200mW peak power in that 50 ohms... vs 5mW in 10mA drive.
  • jmg wrote: »
    cgracey wrote: »
    jmg wrote: »
    cgracey wrote: »
    Here's my HDMI test setup. I got a little breakout board on Amazon with screw terminals:
    Does that have resistors for the 10mA HDMI current drive ?

    Just straight connections. Do you think we need resistors at 250 megahertz?

    Yes, I would start with a 'correct' HDMI drive, which is 10mA (500mV into far end's 50 Ohms) & if that works, then you can see if it tolerates a full 3V3 swing.
    3v3 is likely to be outside the common mode range of any receiver, not to mention you are asking P2 to sink up to ~ 66mA if driving that 50 Ohms direct, and you are above 200mW peak power in that 50 ohms... vs 5mW in 10mA drive.

    270 ohm series resistor, then?
  • jmgjmg Posts: 14,244
    TonyB_ wrote: »
    270 ohm series resistor, then?
    Yes.

  • For testing you may be able get by with 0.1uF coupling caps on all 8 TMDS lines. This works with Lattice FPGAs on 3 of my DVI/HDMI monitor devices at least and I think the signal there is 3.3Vpp. But the closer you can get to a real CML interface the better, otherwise you might be spending time debugging signal integrity stuff not the protocol.
  • cgraceycgracey Posts: 12,440
    edited 2018-10-25 - 23:43:18
    I could just use the 123.75-ohm DAC in digital output mode. That would be like having 123.75-ohm resistors in series with the I/O pins. Do you guys think that would be okay?
  • jmgjmg Posts: 14,244
    cgracey wrote: »
    I could just use the 123.75-ohm DAC in digital output mode. That would be like having a 123.75-ohm resistor in series with an I/O pin. Do you guys think that would be okay?

    Try both. Start with the simplest, and if that works, you can try other ideas until something breaks (hopefully, not irreversibly ;) )
  • jmg wrote: »
    cgracey wrote: »
    I could just use the 123.75-ohm DAC in digital output mode. That would be like having a 123.75-ohm resistor in series with an I/O pin. Do you guys think that would be okay?

    Try both. Start with the simplest, and if that works, you can try other ideas until something breaks (hopefully, not irreversibly ;) )

    I calculate the internal resistance of 123.75 ohm will give ~950mV differential voltage at the receiver, which is less than 1200mV max (DC) in the spec. Give it a go!
  • Super! Will do.
  • TonyB_TonyB_ Posts: 1,414
    edited 2018-10-30 - 01:44:25
    Although this is probably irrelevant at this time, CML drivers for DVI/HDMI are open-collector. Will the DAC mode be slower than an OC?

    One last comment today about the 10-bit control codes output during blanking. DVI mode is simpler than HDMI and this is how I think it works:
    CTL0 = 1101010100	Output this always on R & G channels
    			HSync & Vsync inactive on B channel 
    
    CTL1 = 0010101011 	Hsync active on B channel
    
    CTL2 = 0101010100 	Vsync active on B channel
    
    CTL3 = 1010101011 	Hsync & Vsync active on B channel
    
  • jmgjmg Posts: 14,244
    TonyB_ wrote: »
    Although this is probably irrelevant at this time, CML drivers for DVI/HDMI are open-collector. Will the DAC mode be slower than an OC?

    It could be a good idea to test both CMOS and open collector.
    CMOS will have more predictable tr/tf, but open collector could allow users to modify Vio, at least a little, and it gives 3v3 miss-match tolerance.
    There are still clamp diodes present, so Vio would not want be set below ~ 2.7V, in open collector.

  • cgraceycgracey Posts: 12,440
    edited 2018-10-26 - 08:11:16
    It works!

    I've got the P2 generating the data in memory, then streaming out only three different lines:

    1) display line
    2) hidden line
    3) hidden line with VSYNC

    It's pumping out the 8-bit patterns of {R+, R-, G+, G-, B+, B-, CLK+, CLK-} at 250MHz and one of my desk displays is taking it in, without any special resistors or drive levels - just CMOS outputs.

    HDMI_test.jpg

    Here's the code that implements, in software, the hardware TMDS algorithm that will be in the next silicon (and much simpler to use). If any of you with a P2 hook P[7:0] to an HDMI connector, this program will generate a display:
    con		base		= $1000			'base address of line bytes
    		lineticks	= 800			'ticks per line
    		linebytes	= lineticks * 10	'*10 for 10b output per tick
    '
    '
    ' HDMI display test for early P2 silicon with 20MHz crystal and
    ' P[7:0] connected to HDMI {R+, R-, G+, G-, B+, B-, CLK+, CLK-}
    '
    ' The next version of silicon will have TMDS hardware to compose LVDS stream on the fly.
    '
    dat		org
    
    		hubset	##%1_000001_0000011000_1111_10_00	'enable crystal+PLL, stay in 20MHz+ mode
    		waitx	##20_000_000/100			'wait ~10ms for crystal+PLL to stabilize
    		hubset	##%1_000001_0000011000_1111_10_11	'now switch to PLL running at 250MHz
    
    		setxfrq	##$80000000		'set streamer to output on every clock
    
    		mov	dira,#$FF		'P[7:0] = {R+, R-, G+, G-, B+, B-, CLK+, CLK-}
    '
    '
    ' Write visible line into hub
    '
    vline		wrfast	#0,line_vis		'ready to write line data
    
    		mov	bal_r,#0		'reset balance accumulators
    		mov	bal_g,#0
    		mov	bal_b,#0
    
    		mov	z,##640			'write visible pixels
    .prep		callpa	#0*256/3,#pretty
    		setbyte	rgb,pa,#3
    		callpa	#1*256/3,#pretty
    		setbyte	rgb,pa,#2
    		callpa	#2*256/3,#pretty
    		setbyte	rgb,pa,#1
    		call	#convert_rgb
    		djnz	z,#.prep
    
    		mov	z,#16			'write pre-hsync
    .hpre		mov	color_r,sync0
    		mov	color_g,sync0
    		mov	color_b,sync0
    		call	#output_rgb
    		djnz	z,#.hpre
    
    		mov	z,#16			'write hsync
    .hsync		mov	color_r,sync0
    		mov	color_g,sync0
    		mov	color_b,sync1
    		call	#output_rgb
    		djnz	z,#.hsync
    
    		mov	z,#128			'write post-sync
    .hpost		mov	color_r,sync0
    		mov	color_g,sync0
    		mov	color_b,sync0
    		call	#output_rgb
    		djnz	z,#.hpost
    '
    '
    ' Write invisible line into hub
    '
    iline		mov	z,##640+16
    .hpre		mov	color_r,sync0
    		mov	color_g,sync0
    		mov	color_b,sync0
    		call	#output_rgb
    		djnz	z,#.hpre
    
    		mov	z,#16
    .hsync		mov	color_r,sync0
    		mov	color_g,sync0
    		mov	color_b,sync1
    		call	#output_rgb
    		djnz	z,#.hsync
    
    		mov	z,#128
    .hpost		mov	color_r,sync0
    		mov	color_g,sync0
    		mov	color_b,sync0
    		call	#output_rgb
    		djnz	z,#.hpost
    '
    '
    ' Write sync line into hub
    '
    sline		mov	z,##640+16
    .hpre		mov	color_r,sync2
    		mov	color_g,sync2
    		mov	color_b,sync2
    		call	#output_rgb
    		djnz	z,#.hpre
    
    		mov	z,#16
    .hsync		mov	color_r,sync2
    		mov	color_g,sync2
    		mov	color_b,sync3
    		call	#output_rgb
    		djnz	z,#.hsync
    
    		mov	z,#128
    .hpost		mov	color_r,sync2
    		mov	color_g,sync2
    		mov	color_b,sync2
    		call	#output_rgb
    		djnz	z,#.hpost
    '
    '
    ' Output screen data over and over
    '
    		rdfast	line_cnt,line_vis	'ready to loop-read visible line buffer
    
    .field		mov	x,#480			'ready for 480 visible lines
    .vis		xcont	line_mod,#3		'output visible line
    		cmp	x,#1		wz	'if last line, update fblock to invisisble line
    	if_z	fblock	line_cnt,line_inv
    		djnz	x,#.vis
    
    		mov	x,#10			'ready for 10 invisible lines
    .pre		xcont	line_mod,#3		'output visible line
    		cmp	x,#1		wz	'if last line, update fblock to sync line
    	if_z	fblock	line_cnt,line_syn
    		djnz	x,#.pre
    
    		mov	x,#2			'ready for 2 sync lines
    .sync		xcont	line_mod,#3		'output visible line
    		cmp	x,#1		wz	'if last line, update fblock to invisisble line
    	if_z	fblock	line_cnt,line_inv
    		djnz	x,#.sync
    
    		mov	x,#33			'ready for 33 invisible lines
    .post		xcont	line_mod,#3		'output visible line
    		cmp	x,#1		wz	'if last line, update fblock to visisble line
    	if_z	fblock	line_cnt,line_vis
    		djnz	x,#.post
    
    		jmp	#.field
    '
    '
    ' Make pretty color from pa and z into x
    '
    pretty		mov	x,z
    		sca	x,##round(256.0/480.0 * float($10000))
    		add	pa,0
    		shl	pa,#24
    		qrotate	#127,pa
    		getqx	pa
    	_ret_	bitnot	pa,#7
    '
    '
    ' Data
    '
    sync0		long	%1101010100		'
    sync1		long	%0010101011		'	 hsync
    sync2		long	%0101010100		'vsync
    sync3		long	%1010101011		'vsync + hsync
    
    line_mod	long	$1080<<16 + linebytes	'RFBYTE streamer mode
    line_cnt	long	linebytes / 64	
    
    line_vis	long	base + linebytes*0	'visible line address
    line_inv	long	base + linebytes*1	'invisible line address
    line_syn	long	base + linebytes*2	'sync line address
    '
    '
    ' Convert 8:8:8:0 RGB into 10-byte TMDS pattern in hub
    '
    convert_rgb	getbyte	color,rgb,#3
    		mov	bal,bal_r
    		call	#color_tmds
    		mov	bal_r,bal
    		mov	color_r,color
    
    		getbyte	color,rgb,#2
    		mov	bal,bal_g
    		call	#color_tmds
    		mov	bal_g,bal
    		mov	color_g,color
    
    		getbyte	color,rgb,#1
    		mov	bal,bal_b
    		call	#color_tmds
    		mov	bal_b,bal
    		mov	color_b,color
    
    output_rgb	mov	x,#0
    .loop		shr	color_r,#1	wc
    		bitc	y,#7
    		bitnc	y,#6
    		shr	color_g,#1	wc
    		bitc	y,#5
    		bitnc	y,#4
    		shr	color_b,#1	wc
    		bitc	y,#3
    		bitnc	y,#2
    		cmp	x,#5		wc
    		bitc	y,#1
    		bitnc	y,#0
    		wfbyte	y
    		incmod	x,#9		wc
    	if_nc	jmp	#.loop
    
    		ret
    '
    '
    ' Convert R/G/B in color[7:0] into TMDS in color[9:0]
    '
    color_tmds	ones	bal_m,color		'ones > 4 || ones == 4 && !color[0]?
    		cmp	bal_m,#4	wcz
    	if_z	testb	color,#0	wc	'c=0 for XNOR
    
    		testb	color,#0	wz
      if_z_eq_c	bitnot	color,#1
    	
    		testb	color,#1	wz
      if_z_eq_c	bitnot	color,#2
    	
    		testb	color,#2	wz
      if_z_eq_c	bitnot	color,#3
    	
    		testb	color,#3	wz
      if_z_eq_c	bitnot	color,#4
    	
    		testb	color,#4	wz
      if_z_eq_c	bitnot	color,#5
    	
    		testb	color,#5	wz
      if_z_eq_c	bitnot	color,#6
    	
    		testb	color,#6	wz
      if_z_eq_c	bitnot	color,#7
    
    		ones	bal_m,color		'get bal_m
    
    		bitc	color,#8
    
    		sub	bal_m,#4	wcz	'sign of bal_m into c, (bal_m == 0) into z
    
    	if_nz	cmp	bal,#0		wz	'get (bal_m == 0 || bal == 0) into z
    
    		testbn	bal,#31		xorc	'get (bal_m[31] == bal[31]) into c
    		wrc	bal_sign		'get (bal_m[31] == bal[31]) into bal_sign
    
    	if_z	testbn	color,#8	wc	'inv_m = bal_zero ? !m[8] : bal_sign
    
    		bitc	color,#9		'finalize TMDS pattern
    	if_c	xor	color,#$FF
    
    		shl	bal_m,#1		'adjust bal
    
    		testbn	color,#8	wc	
    	if_z	jmp	#.sum
    
    		testb	bal_sign,#0	wc
    		testb	color,#8	wz
      if_c_eq_z	sumnc	bal,#2
    .sum	_ret_	sumc	bal,bal_m
    '
    '
    ' Data
    '
    color		res	1
    bal		res	1
    bal_m		res	1
    bal_sign	res	1
    
    bal_r		res	1
    bal_g		res	1
    bal_b		res	1
    
    color_r		res	1
    color_g		res	1
    color_b		res	1
    
    rgb		res	1
    
    x		res	1
    y		res	1
    z		res	1
    t		res	1
    
    1152 x 2048 - 690K
  • cgraceycgracey Posts: 12,440
    edited 2018-10-26 - 08:09:44
    Here is the heart of the P2 HDMI test:
    '
    '
    ' Output screen data over and over
    '
    		rdfast	line_cnt,line_vis	'ready to loop-read visible line buffer
    
    .field		mov	x,#480			'ready for 480 visible lines
    .vis		xcont	line_mod,#3		'output visible line
    		cmp	x,#1		wz	'if last line, update fblock to invisisble line
    	if_z	fblock	line_cnt,line_inv
    		djnz	x,#.vis
    
    		mov	x,#10			'ready for 10 invisible lines
    .pre		xcont	line_mod,#3		'output visible line
    		cmp	x,#1		wz	'if last line, update fblock to sync line
    	if_z	fblock	line_cnt,line_syn
    		djnz	x,#.pre
    
    		mov	x,#2			'ready for 2 sync lines
    .sync		xcont	line_mod,#3		'output visible line
    		cmp	x,#1		wz	'if last line, update fblock to invisisble line
    	if_z	fblock	line_cnt,line_inv
    		djnz	x,#.sync
    
    		mov	x,#33			'ready for 33 invisible lines
    .post		xcont	line_mod,#3		'output visible line
    		cmp	x,#1		wz	'if last line, update fblock to visisble line
    	if_z	fblock	line_cnt,line_vis
    		djnz	x,#.post
    
    		jmp	#.field
    

    So, this code streams out bytes from the FIFO at full blast, on every clock, and the address and block size can be changed on the fly using FBLOCK, to switch between buffers that are being streamed out. You could output 32 bits per clock, as well, if you wanted. And every cog could do the same concurrently,

    I think this HDMI thing is done. Now, I'm going to see about clock gating to get dynamic power consumption down.
  • Nice!

    Looks simple, clean, easy to understand. Nice work Chip.
  • jmgjmg Posts: 14,244
    cgracey wrote: »
    It works!
    ...
    It's pumping out the 8-bit patterns of {R+, R-, G+, G-, B+, B-, CLK+, CLK-} at 250MHz and one of my desk displays is taking it in, without any special resistors or drive levels - just CMOS outputs.

    Good result !
    Did you also check the DAC in output mode, and a 270 Ohm series R, and also a 0.1uF in series with 270R as mentioned above ?
    The R+C may be a good way to get some extra supply tolerance, and avoid phantom power effects.
  • jmg wrote: »
    cgracey wrote: »
    It works!
    ...
    It's pumping out the 8-bit patterns of {R+, R-, G+, G-, B+, B-, CLK+, CLK-} at 250MHz and one of my desk displays is taking it in, without any special resistors or drive levels - just CMOS outputs.

    Good result !
    Did you also check the DAC in output mode, and a 270 Ohm series R, and also a 0.1uF in series with 270R as mentioned above ?
    The R+C may be a good way to get some extra supply tolerance, and avoid phantom power effects.

    I just needed to know that the digital guts work. They do, without any special analog treatment, so the rest can be sorted later. We"ve got lots of options there.
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