RISC V ?

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  • But that looks like it's about the size of a RISC V core anyway. Judging by the size estimates at the bottom of this page: https://github.com/cliffordwolf/picorv32
  • KeithEKeithE Posts: 930
    edited October 11 Vote Up0Vote Down
    Heater. wrote: »
    But that looks like it's about the size of a RISC V core anyway. Judging by the size estimates at the bottom of this page: https://github.com/cliffordwolf/picorv32

    Duh - you are correct. Hmm - maybe J1a can be radically shrunk. I would have to synthesize to be sure, but I'm guessing this might be related the stacks being implemented as registers.

    stack2 #(.DEPTH(15)) dstack(.clk(clk), .rd(st1), .we(dstkW), .wd(st0), .delta(dspI));
    stack2 #(.DEPTH(17)) rstack(.clk(clk), .rd(rst0), .we(rstkW), .wd(rstkD), .delta(rspI));


    That's (15+1)*16 + (17+1)*16 = 544 registers if I count correctly. (The +1 is for the head register.)
  • So ignoring the RAM you could fit 4.5 of those on the UP5K part.

    No need to do that, I think, the Ultra Plus has 4 blocks of 16 kBytesx16 single port RAM, the J1 is a 16 bit implementation, one could have 4 with their own 16 kWords of memory.

    There is Ataradov's RISCV implementation, it is pipelined too and not much bigger than PicoRISC V.
    In terms of LUTS it seems smaller than the 8051 we use at work.
  • Cluso99Cluso99 Posts: 13,913
    edited October 14 Vote Up0Vote Down
    There is a home brew micro built from 12 FLASH/EEPROMS and an SRAM. Quite an interesting design. It's in the home brew computer ring (not sure of the precise name but I'm sure google will find it). Some of the EPROMs are just emulating latches.

    I am sure this could be modified to make it RISC V.
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • FWIW I have just been blown away looking for a video card. The Nvidia RTX 2080 Ti has >4000 CUDA cores.
    Didn't realise just how many cores these graphics cards are packing!!!
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • Mind bending isn't it.

    And now Nvidea is working on a RISC V core to put in there and manage all of those little guys.
  • Cluso,
    The "cuda core" numbers are a bit misleading. While it is true that they have that many scalar floating point operation units, it's a bit of a stretch to call them cores in the same sense that you are thinking of cores. For RTX, these "cuda cores" are grouped together into Streaming Multiprocessors (SMs). One SM has 4 "Warp Scheduler" groups, each group has a a warp scheduler and dispatch unit, a register file, 16 int32 units, 16 fp32 units, 4 load/store units, 2 tensor cores (again not really a true core), and a Special Function Unit (this is for things like trig, and what not). The SM also has a block of shared memory (shared by all 4 groups, and also is the L1 cache to main memory (it's split between those two things), 4 texture sampling units, and an RT Core (again not a true core). Then, 12 SMs are grouped together into a GPC (Graphics Processing Unit), the GPC also has some raster engine stuff and is hooked to the P2 cache and the memory controllers (that connect to the external GDDR). Any given GPU will have at least 1 GPC, the high end ones have 6 of them.

    nvidia equates the fp32 operations as cuda cores, so there are 64 of those per SM and 72 SMs, you get 4608 "cuda cores" in the top end cards.

    So, it's probably more correct to call an SM a core, or perhaps one of the warp groups inside the SM a core. If you go with SM, then the top card has 72 of them, if you go with the warp group, then it has 288 of them.

    To relate this to Prop2, a warp group would be a cog with it's register file being cog/lut memory. The shared memory would be like hub. So, an SM is like a 4 cog Prop2, but then a GPC has 12 of those and they all connect to an external shared memory (really 12 banks of external memory that can all be accessed simultaneously by different SMs/GPCs). They don't really have an equivalent to the smart pins, nor any real I/O besides to the external memory.
  • About the riscv softcore contest :
    I played a bit, got zephyr running and the required RV32I compliance test passing on a 4 stages VexRiscv, and it require "many" CSR :
    mstatus + mie + mie + catch missaligned branch/load/store + the following :
    misaExtensionsInit = 0,
    misaAccess = CsrAccess.READ_ONLY,
    mtvecAccess = CsrAccess.WRITE_ONLY,
    mepcAccess = CsrAccess.READ_WRITE,
    mscratchGen = true,
    mcauseAccess = CsrAccess.READ_ONLY,
    mbadaddrAccess = CsrAccess.READ_ONLY,
    mcycleAccess = CsrAccess.NONE,
    minstretAccess = CsrAccess.NONE,
    ecallGen = true,
    ebreakGen = true,
    wfiGenAsNop = true,

    It nearly double the size of the CPU on ice40, as in those FPGA if you just want a FF you lose the LUT.
    minimal
    iCE40 -> 1423 LC
    Artix 7 -> 728 LUT 533 FF
    Cyclone V ->544 ALMs
    Cyclone IV -> 997 LUT 461 FF

    A RV32I configuration with reduced CSR to emulate all the missing feature would require :
    iCE40 ->1114 LC
    Artix 7 -> 586 LUT 403 FF
    Cyclone V -> 427 ALMs
    Cyclone IV -> 818 LUT 329 FF
  • I'm surprised that the competition does not allow the RV32E for the small category. That is "E" as in "embedded", intended for small systems. It only has 16 registers and does not require all those counters.
  • RV32E isn't ready yet as there is no compiler support. Zephyr only require one timer (64 bits :( ), the compliance tests doesn't require any counter
  • I mean, the current Zehyr port require one 64 bit counter / comparator ^^
    Could be change without much pain.
  • I was wondering about the status of GCC support for RV32E. I found a commit log in GCC that says: "RISC-V: Add RV32E support.". I guess none of that is upstreamed yet.

    https://github.com/riscv/riscv-gcc

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