Fozzie on a pin

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  • Tubular wrote: »
    Couple on new extreme benchmarks for NTSC silicon fozzie:-

    Lowest clock rate: 7.16129 MHz - 12mA at 5v, 1 minion cog
    Highest clock rate: 348 MHz - 540 mA at 5v, 4 minion cogs

    We tried several different divisors for 348 MHz, a lot of weird stuff happens at the step immediately afterwards (eg 350 MHz has 'half a fozzie') etc.
    That might be the 1.8V 1A regulator giving up, rather than the Prop2 losing it.

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  • yep. the absolute limit seems to be twice 3.57MHz, that 7.16 is mighty close to it, and is obtained with dividing by 62 and multiplying by 37 from a 12MHz crystal oscillator


  • Tubular wrote: »
    Couple on new extreme benchmarks for NTSC silicon fozzie:-

    Lowest clock rate: 7.16129 MHz - 12mA at 5v, 1 minion cog
    Highest clock rate: 348 MHz - 540 mA at 5v, 4 minion cogs

    We tried several different divisors for 348 MHz, a lot of weird stuff happens at the step immediately afterwards (eg 350 MHz has 'half a fozzie') etc.

    With the way logical paths are optimized in the chip, you should see a wall of failure at some frequency.
  • Yeah, no matter what PLL divisor we used, things fell apart at the step above 348 MHz. Yet 348 using any divisor is pretty steady, eg 4*87, 6 * 58, 12 * 29 etc.
  • Tubular wrote: »
    Yeah, no matter what PLL divisor we used, things fell apart at the step above 348 MHz. Yet 348 using any divisor is pretty steady, eg 4*87, 6 * 58, 12 * 29 etc.

    That seems like a GOOD sign. You need another 200mV of VDD, though.
  • cgraceycgracey Posts: 10,565
    edited October 8 Vote Up0Vote Down
    Did you coordinate your attempts with the freeze spray?
  • TubularTubular Posts: 3,296
    edited October 8 Vote Up0Vote Down
    Yeah. Freeze spray is the magic crank handle that gets it past an early lockup. Once the thing runs, it tends to keep running.

    Our new high record is 372 MHz, obtained with divisor 1 and multiplier 31, from a 12 MHz xtal OSC. We have to pre-freeze the board before hitting F11.

    You're right about the 'wall of failures'. Brian uses 1..4 cogs (configurable in pnut source) to split up the picture according to chunky vertical regions. So if you have 4 minions, first minion does the top quarter, minion 4 does bottom quarter.

    On the borderline failure case, we observed the top and bottom quarters (just) copying some pixels, the middle two weren't, and the cordic jittering but not really rotating successfully.

    Current at 372 MHz was 572mA on the 5v rail.

    It feels a bit like launch launching saturn rockets - freeze spray, waiting for the ice to dissipate a bit, a countdown and then hitting F11 while I watch current and Brian watches the NTSC screen. There are a few "stages" - the current initially from 30 to about 40ma, then jumps to about 510mA, before "final stage" hits 572mA. But if it gets to final stage it tends to keep running.

    From the final stage, we even tried hitting it with a hair dryer, but the airflow seems to assist rather than heat the heatsink
  • And yes, if you wanted to go further that extra 200mV on the 1v8 rail would help, and you're right about the peltier and a 'pre-cooling' to get past that early lockup hurdle. It was interesting that early lockup seemed to be near the start (PLL engagement?)

  • Can you get VDD to 2.0V? The chip is spec'd to run at 2.0V.
  • I don't think we can inject 2v, unless we remove the switching reg, but let me investigate further.

    We broke down the code and the big hurdle seems to be the initial clkset. Also we were launching 7 cogs in very short succession afterwards, and spacing it out might be enough.

    However we did get the PLL running at 384 MHz successfully (without launching any further cogs)

    Power supply wise, on that clkset we're going from 30mA to 500mA (on the 5v rail), which is like 1.4A on the 1v8 rail, which is more than the regulator is rated to. We're probably just asking too much.
  • evanh wrote: »
    Tubular wrote: »
    Couple on new extreme benchmarks for NTSC silicon .........
    That might be the 1.8V 1A regulator giving up, rather than the Prop2 losing it.

    I think you're right, Evanh. Didn't realise this until later, we're asking an awful lot of a 1A regulator.
    Torex do some bigger ones (xcl214, xcl212) but the footprint gets a bit uglier.

    The other thing we didn't try is a big cap or supercap on the 1v8 rail, to help that ~80 to 1400mA sudden transition
  • WOW!!! That's a fantastic set of results.

    Are you using a 12MHz crystal or oscillator? Think I have a few 3225 crystals at other frequencies
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  • Yes, its 12 MHz. you'd have to check with Peter whether its an xtal or an osc, they look similar from above : )

  • actually, its probably a crystal, as the board seems to take zero current then the P2 isn't doing anything. An osc might take a few mA.
  • Peter JakackiPeter Jakacki Posts: 7,872
    edited October 8 Vote Up0Vote Down
    That 12MHz part is a 10ppm oscillator and the datasheet indicates 7ma max. The crystal pads are the big ones which the 1.8V rail runs through.

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  • Very interesting discussion. Start-up of a Saturn rocket, indeed. :)

    Big comfort to see fozzie bear spin on a real chip, cordic and all. A whole lot has to be right for that to happen.
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