Good to see multiple cores getting more 'air time' in the Microcontroller space.
This is more loosely coupled than a P1, it's really more like two MCUs in one package, each with some peripherals, and FIFO/Mailbox interfaces between the 2 cores.
The P2 has much larger and common shared memory, and any P2 Core can access any Smart Pin cell peripheral.
Still, this applies even better to P2
“Customers tell us one of their biggest challenges is integrating software from multiple teams where one team is focused on the time-critical control code and another is working on the rest of the application,” said Joe Thomsen, vice president of Microchip’s MCU16 business unit. “We created this dual-core product to simplify that software integration and optimize the performance for math-intensive applications.”
Strange they tag one core as 90MHz and the other as 100MHz ? They do seem to have two (four?) PLLs, making the cores quite independent clock domains.
PLL rules : For PLL operation, the following requirements must be met at all times without exception:
• The PLL Input Frequency (FPLLI) must be in the range of 8 MHz to 64 MHz
• The PFD Input Frequency (FPFD) must be in the range of 8 MHz to (FVCO/16) MHz
• The VCO Output Frequency (FVCO) must be in the range of 400 MHz to 1600 MHz
So how fast can parts of this chip clock ?
Find this "Note: DAC input frequency needs to be 500 MHz."
- note that's a PDM + RC filter type DAC, so needs a high clock, still 500MHz is impressive.
SPI says 2~32b, 50MHz (or 40MHz or 15/9MHz, varies in data) (but no QuadSPI ? )
i2c Max 1MHz
UARTS - has 19:0b Divisor, and says
1 = Uses fractional Baud Rate Generation
0 = Uses legacy divide-by-x counter for baud clock generation (x = 4 or 16 depending on the BRGH bit)
BCLKSEL<1:0>: Baud Clock Source Selection bits
11 = Reserved
10 = FOSC
01 = Reserved
00 = FOSC/2 (FP)
Fosc is harder to nail down, but seems to be faster than the CPU clock, Fcy is FOsc/2 thru FOsc/2/128 in doze mode.
Looks like Fosc = Fpllo/2 is possible, where Fpllo is FVCO/(1~7)(1~7) - examples in data are 200MHz,240MHz,300MHz,400MHz for /2 = 100MHz~200MHz indicated Baud/Timer clocks ?
Clocking looks complex, and not easy to be sure you have not overclocked some peripheral.