Prop2 FPGA files!!! - Updated 2 June 2018 - Final Version 32i

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  • jmgjmg Posts: 13,933
    TonyB wrote: »
    Instructions v19 say {WC/WZ/WCZ} but C and Z are part of the rotates.
    A smarter question is, are all those suffixes valid ?
    WCZ would be the most common usage, but if WC and WZ are operationally correct, then they do belong in the opcode set.

  • cgraceycgracey Posts: 11,711
    edited 2017-05-24 - 00:23:01
    TonyB wrote: »
    cgracey wrote: »
    The XORO32 instruction iterates the state, but to actually get the random number out, you need to add the low and high 16-bit fields and use bits 15..1 of the sum, ignoring bit 0. So, just calling it RANDOM would be too simplistic.

    Well, XORO32 will mean nothing to newbies, like me, especially when they find out that XORO16+16 would be more accurate.

    Good point. We just used the naming precedent from xoroshiro128+. At first, I named it XORO32P, but that seemed twice as complex as XORO32.
  • I've got the doc's updated to cover XBYTE and RFVAR{S}.
  • Is v19 the final FPGA image other than maybe fixing some bugs?
  • David Betz wrote: »
    Is v19 the final FPGA image other than maybe fixing some bugs?

    It seems there's some smart pin fine-tuning going on. Chip gave a two month window, so...
  • Seairth wrote: »
    David Betz wrote: »
    Is v19 the final FPGA image other than maybe fixing some bugs?

    It seems there's some smart pin fine-tuning going on. Chip gave a two month window, so...
    Two months before image freeze? I guess there won't be any P2 chips this year...
  • David Betz wrote: »
    Seairth wrote: »
    David Betz wrote: »
    Is v19 the final FPGA image other than maybe fixing some bugs?

    It seems there's some smart pin fine-tuning going on. Chip gave a two month window, so...
    Two months before image freeze? I guess there won't be any P2 chips this year...

    His exact statement was
    cgracey wrote: »
    It's going to be a few months, probably, before we start spending the money to fabricate, so there's time to make sure the smart pins have what they ought to.

    Interpret as desired.
  • Seairth wrote: »
    David Betz wrote: »
    Seairth wrote: »
    David Betz wrote: »
    Is v19 the final FPGA image other than maybe fixing some bugs?

    It seems there's some smart pin fine-tuning going on. Chip gave a two month window, so...
    Two months before image freeze? I guess there won't be any P2 chips this year...

    His exact statement was
    cgracey wrote: »
    It's going to be a few months, probably, before we start spending the money to fabricate, so there's time to make sure the smart pins have what they ought to.

    Interpret as desired.
    Thanks for reminding me of what Chip said. It sounds like the instruction set should be final in any case. I've got v19 loaded on my P123/A9 board and ready to go!

  • He said smart pin tweaks should not impact software development.

    The intent here is to not break tool building. :D
    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: https://forums.parallax.com/discussion/123709/commented-graphics-demo-spin<br>
  • Does anyone have a convenient link to the P2 serial loader protocol documentation?
  • Seairth wrote: »
    Does anyone have a convenient link to the P2 serial loader protocol documentation?
    I think it's in the same document that describes the rest of P2 linked to in the first message of this thread.

  • Seairth wrote: »
    Does anyone have a convenient link to the P2 serial loader protocol documentation?

    Dave Hein has made a working loader program. Most recent sources posted here - http://forums.parallax.com/discussion/comment/1409237/#Comment_1409237 You'll get good details from those.

    A small patch is required for v19 as per this - http://forums.parallax.com/discussion/comment/1411885/#Comment_1411885
    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • This may be a bit premature to ask, but considering the recently improved Fmax for the FPGAs, does that mean that the Fmax for the final silicon will also be faster than earlier estimates? If that's true, what is the new target speed?
  • jmgjmg Posts: 13,933
    Seairth wrote: »
    This may be a bit premature to ask, but considering the recently improved Fmax for the FPGAs, does that mean that the Fmax for the final silicon will also be faster than earlier estimates? If that's true, what is the new target speed?

    I like your optimism.... :)
    I was taking the improved FPGA specs, as simply upping the chances of even meeting the targets...
    'Better guesses' will not really be possible, until after the masks are routed.
  • That's a tad pessimistic there JMG. The answer is a yes for sure. Of course there wasn't a solid baseline in the first place, Chip only ever previously guessed at 160 MHz, so we will never really know the extent of improvement.
    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • There we go. More optimism without any more certainty. :D
    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • I don't know what the silicon Fmax will be, but I think the design should close at 160MHz, at least.
  • jmgjmg Posts: 13,933
    There is this news....
    "SiFive's Freedom E310 MCU is implemented in the TSMC 180G process, runs at better than 300 MHz, Operating Voltage: 3.3 V and 1.8 V"

    I think 180G is TSMC 180nm, General purpose, so the indications are reasonable cores can do good MHz numbers at 180nm.
    P2 is larger, and has larger, and thus slower, on Chip RAM, so maybe 160 MHz is realistic ?
  • kwinnkwinn Posts: 8,329
    edited 2017-05-30 - 22:40:01
    In science there is no authority. There is only experiment.
    Life is unpredictable. Eat dessert first.
  • I think it's reasonable to think​ that before we had "dunno" and now we have "dunno + a smidgen".
  • The synthesis will tell us a lot. Until then, we got wants and hopes!

    Testing...
    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: https://forums.parallax.com/discussion/123709/commented-graphics-demo-spin<br>
  • There is a new v19a at the top of this thread which has a file for the Prop123-A9 that includes all 64 smart pins with 8 cogs and 1024KB hub RAM. This was per Ozpropdev's request.
  • jmgjmg Posts: 13,933
    cgracey wrote: »
    There is a new v19a at the top of this thread which has a file for the Prop123-A9 that includes all 64 smart pins with 8 cogs and 1024KB hub RAM. This was per Ozpropdev's request.
    Cool.
    Does that mean it's then possible to build an example of 32 UART TX chained to 32 UART RX and manage 4 pairs per COG, and then 'let it rip' to see what baud rates can be sustained ?
    Digikey shows 318 items under UART 4,8 Chans, and cheapest 4ch is ~$5, 8ch is ~$11 Top speed is 31.25Mbps
    Exar have a FS-USB-Quad uart for ~ $4
  • cgraceycgracey Posts: 11,711
    edited 2017-06-01 - 00:34:05
    jmg wrote: »
    cgracey wrote: »
    There is a new v19a at the top of this thread which has a file for the Prop123-A9 that includes all 64 smart pins with 8 cogs and 1024KB hub RAM. This was per Ozpropdev's request.
    Cool.
    Does that mean it's then possible to build an example of 32 UART TX chained to 32 UART RX and manage 4 pairs per COG, and then 'let it rip' to see what baud rates can be sustained ?
    Digikey shows 318 items under UART 4,8 Chans, and cheapest 4ch is ~$5, 8ch is ~$11 Top speed is 31.25Mbps
    Exar have a FS-USB-Quad uart for ~ $4

    Yes, you could use pairs of pins, where one outputs and the other inputs from it, using the A-input mux to select its neighbor's output. Interesting about multi-UART chip costs.
  • cgracey wrote: »
    There is a new v19a at the top of this thread which has a file for the Prop123-A9 that includes all 64 smart pins with 8 cogs and 1024KB hub RAM. This was per Ozpropdev's request.
    Much appreciated Chip!
    Thanks :)

    Melbourne, Australia
  • Wow... and thank you for asking!!!
  • Anyone know if PNut has any command line options? Namely for compiling and exiting without GUI. I just bumped into Peter J's question http://forums.parallax.com/discussion/comment/1380508/#Comment_1380508 on this matter but not sure if it was ever followed through on.
    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • evanh wrote: »
    Anyone know if PNut has any command line options? Namely for compiling and exiting without GUI. I just bumped into Peter J's question http://forums.parallax.com/discussion/comment/1380508/#Comment_1380508 on this matter but not sure if it was ever followed through on.

    Nope.
  • I tried running PNut from the command line with various arguments and the only thing it seem to understand was a source file name. So you can do "PNut_v19 file.spin2" and it will open file.spin2. I couldn't get it to initiate an F11 or anything else from the command land. AFAIK F11 still has to be issued manually.

    I did write a P2 assembler and loader that can do the same functionality as F11 in PNut. They are part of the p2gcc tool set, and are posted in the Can't Wait for PropGCC on the P2? thread.
  • loadp2 is much appreciated. I'm even using the auto terminal mode for emitting debugging strings.

    I'm a tad hesitant to try the compiler/assembler though, as my aim is to critique Chip's latest work.
    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
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