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What is the Prop2 good for? — Parallax Forums

What is the Prop2 good for?

I just heard about this new speaker https://indiegogo.com/projects/a-speaker-the-speaker-that-only-you-can-hear#/ and I think it's similar to a phase delay array radar system. It looks we have ultrasound to locate the listner and then direct the sound beam to him. Now, what can the prop do with 64 ADC and DAC? I can imagine such a system to be a perfect application for P2's, why stop with one chip, if the can be cascaded easily. Happy thinking, ErNa

Comments

  • cgraceycgracey Posts: 13,378
    edited 2016-03-15 23:00
    When I saw the thread, I was worried someone was going to answer the question with something like "heating element". That can't even be claimed, yet, though.

    To what ErNa said, I look forward to playing with DSP. Having instant and high-frame rate graphics to show internal workings will be great. Arrays of microphones and transducers have all kinds of interesting possibilities.
  • I think the universal pin setup (adc, current source etc) is going to be really good.

    It's also quite fun to program in pasm.

    Here's the previous thread on other plans people have
    http://forums.parallax.com/discussion/159709/what-will-you-make-with-your-p2
  • Cluso99Cluso99 Posts: 17,437
    Tubular wrote: »
    ...
    It's also quite fun to program in pasm.
    ...

    A 512KB hubexec pasm program might be fun!
    The compiler will no doubt need to be souped up to handle this size tho' ;)

    BTW I have noticed there are a few disillusioned Pi Zero fans out there who cannot get I/O to work reliably (ie deterministically). Need I say more :)
  • kwinnkwinn Posts: 8,684
    Cluso99 wrote: »
    Tubular wrote: »
    ...
    It's also quite fun to program in pasm.
    ...

    A 512KB hubexec pasm program might be fun!
    The compiler will no doubt need to be souped up to handle this size tho' ;)

    BTW I have noticed there are a few disillusioned Pi Zero fans out there who cannot get I/O to work reliably (ie deterministically). Need I say more :)

    P1/P2 hat for the PiZero???
  • 1. Everything I wish the P1 would do, that is, more speed, more I/O
    2. Goertzel for every ADC, that can report in vector terms.. How about an SDR that can decode dozens of signals simultaneously!
    3. Respectably fast CORDIC... Robotic arm kinematics anyone? 'Delta' style 3D printer? 'Swing' style 3D printer? All trivial now!
    4. If I remember right, the DACS have Goertzel for sine wave generation? SDR again, answer all those signals you just decoded!
    5. Revive my solid wooden keyboard idea, the granularity of measurements will be small enough to make it work!
  • Robotic arm kinematics anyone?

    Coooool!
  • BTW, If you enclosed the crystal and chip, and had a simple application, you could throw cogs into endless loops, or stop them to literally to produce and regulate heat and implement a TXCO. Just sayin'
  • ErNaErNa Posts: 1,491
    That is clever! And could be done already with P1. One way is to have a resistor connected to a pin close to the crystal and regulate the crystal temperature!
  • All the credit goes to the fear/proposal/challenge in Chip's post above.

    *****WARNING***** FACETIOUS COMMENT FOLLOWS*****WARNING******

    Is it too late to propose adding peltier junctions to the smart pins for some cooling, too?
  • kwinn wrote: »
    ..
    P1/P2 hat for the PiZero???

    I did a simple P1 Hat for the RPi2 last year using a DIL P1 but I don't think it could be shrunk down to a PiZero without going to SMT.

    I'm looking forward to do something similar with a P2 when it comes out.
  • War?
  • ErNaErNa Posts: 1,491
    Today I found this: edn-europe.com/news/1000-processor-cores-single-chip-californian-researchers-build-kilocore I post the link to have one find inspiration what can be done with the prop2 and also I find it interesting for technology aspects being discussed.
  • Emulation of popular retro video game consoles! Love to see a Famicom/NES emulation there! :)

    Yes, I know there's the Raspberry Pi, but I prefer a straight-to-user approach, without the OS. :)
  • JRetSapDoogJRetSapDoog Posts: 867
    edited 2016-06-21 12:43
    I first read about that 1000 core processor on Engadget yesterday. I had to chuckle when I read "The university had IBM manufacture the chip on a relatively ancient 32-nanometer process" (emphasis added), considering the P2's introductory 160nm process. But I think that the P2 design will be quite applicable to various projects in terms of the mix of features it brings to the table. It's not too specialized and not too general, so it should find a good niche, whereas that 1000 core processor is currently just a research project. It is interesting, though. But the P2 is being designed with the goal of entering production (possibly with a family of chips). And the Chipmaestro just about has it wrapped up.
  • kwinnkwinn Posts: 8,684
    Parallel processing and multiple cores are definitely the way computing is going but I found this statement in the article interesting.

    "However, to make use of available packaging, only the central 160 cores have been powered in tests; figures for full-chip performance are presumed to be extrapolations."

    IOW sidestepping the thornier issues involved in making use of so many processors. Easy to put multiple cores on a chip, not so easy to get optimum performance from them.
  • evanhevanh Posts: 10,415
    If I'm reading it correctly, there is some indication the 1000 core design is thermally constrained unless it's run at much reduced speed/voltage. It would seem it's not in a finished state.

    I think they may have just wanted to hit the 1000 mark as a bit of a marketing push.

    It's also very unclear how programs are loaded to each core. I think only 24 of the cores can run programs from the block RAM, the rest have to be preloaded with their exclusive 128 instruction words.
  • evanhevanh Posts: 10,415
    kwinn wrote: »
    Easy to put multiple cores on a chip, not so easy to get optimum performance from them.

    Yeah, the grid approach has its limits for sure. More RAM, less cores is a better balance. Block RAM nicely fills out the growing dark silicon requirement too.
  • TorTor Posts: 2,010
    Notice that those cores can talk to their neighbours, there's no shared memory.. that's the only way to handle massive numbers of cores. Which is why I found the LUT shared-with-neighbour scheme elegant. It's been done before too. That 1000-core system is not the first multi-core system to do this.
  • evanhevanh Posts: 10,415
    I'd say all grid designs use neighbour sharing. The Prop's HubRAM is way superior to that but is also ultimately limited to a small core count.
  • Emulation of popular retro video game consoles! Love to see a Famicom/NES emulation there! :)

    Yes, I know there's the Raspberry Pi, but I prefer a straight-to-user approach, without the OS. :)


    For that use Ultibo (ultibo.org)! Bare metal programming of the Pi series in FreePascal / Lazarus. Perfect for us old Delphi guys. No OS needed, just code and go. I am using it for my Pi based CNC controller GUI + Arduino Due for the CNC motor control (could not wait any longer for a real P2 sadly, hopefully next gen).

    Makes me wonder what it would take to get Laz/FPC to work with the P2 when it comes out... That would be sweet.
  • kwinnkwinn Posts: 8,684
    Tor wrote: »
    Notice that those cores can talk to their neighbours, there's no shared memory.. that's the only way to handle massive numbers of cores. Which is why I found the LUT shared-with-neighbour scheme elegant. It's been done before too. That 1000-core system is not the first multi-core system to do this.

    The first one I can recall was a 16 cpu system done with 8 bit cpu chips and 4 shared ram chips around each cpu. Don't recall what cpu was used or the size of ram chips.
  • Slightly on topic:

    http://www.theverge.com/2016/6/20/11975356/chinese-supercomputer-worlds-fastes-taihulight
    The TaihuLight is comprised of some 41,000 chips, each with 260 processor cores. This makes for a total of 10.65 million cores, compared to the 560,000 cores in America's top machine.

    I believe the US computer is using Intel processors.
  • evanhevanh Posts: 10,415
    edited 2016-06-21 14:17
    AMD based, just tipping ahead of the IBM based one - http://www.top500.org/lists/2016/06/

    EDIT: Although, I suspect some of those are still contracted target sizes rather than actual installed sizes. It can take years to build each one.

    EDIT2: I'm not sure If Intel has ever been at position #1. It would have been very briefly.
  • Bill HenningBill Henning Posts: 6,445
    edited 2016-06-21 17:04
    You mean like

    RoboPi_0831_web.jpg

    http://www.mikronauts.com/raspberry-pi/robopi/

    for example?

    Others coming :)

    (I eagerly await the P2)

    kwinn wrote: »
    Cluso99 wrote: »
    Tubular wrote: »
    ...
    It's also quite fun to program in pasm.
    ...

    A 512KB hubexec pasm program might be fun!
    The compiler will no doubt need to be souped up to handle this size tho' ;)

    BTW I have noticed there are a few disillusioned Pi Zero fans out there who cannot get I/O to work reliably (ie deterministically). Need I say more :)

    P1/P2 hat for the PiZero???

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