I'm happy to report the P1V (Verilog version of the Propeller) is working on the Parallax 1-2-3 FPGA.
My github repository with the necessary changes is here: https://github.com/mindrobots/P1V
I've forked Jac Goudsmit's repository as it appears to be the most up to date repository based on the Parallax corporate P1V repository. Jac has done a nice job of restructuring the Parallax repository and made it very easy to build P1V's for various boards from the same code base. I intend to follow his guide and work within the scaffold he built.
My changes include only the vary basics needed to build a standard P1V that runs on the A7 version of the Parallax 1-2-3 FPGA board as well as a readme.txt file with building and loading instructions.
The P1V uses the 1-2-3 FPGA USB port in RUN mode for programming. You do NOT need a Prop Plug; however, P30 and P31 are not exposed for your use, they are "hard-wired" to the USB port in the FPGA. The used LEDs, GRN0-GRN15 are used as COG activity indicators - GRN0-GRN7 are lit when COG0-COG7 are active, GRN8-GRN15 are lit when the COGs are inactive. P1V pins 0-29 are brought out to the 3.3V I/O header on the board*. Nothing else on the board is connected to the P1V or exposed to the user in this basic configuration.
*EDIT: I just realized I haven't tested to see if these actually are 3.3V I/O pins. They are intended to be but this must be verified. Sorry!
It does require Quartus II v15 in order to build for the A7 FPGA. Total time to build was about 13 minutes on my 8GB I7 laptop w/ SSD - you have the .rbf file in less time but the timing analysis takes a while to run.
Fitter Status Successful - Fri Jul 31 10:41:44 2015
Quartus II 64-Bit Version 15.0.2 Build 153 07/15/2015 SJ Web Edition
Revision Name fpga123
Top-level Entity Name fpga123
Family Cyclone V
Timing Models Final
Logic utilization (in ALMs) 8,523 / 56,480 ( 15 % )
Total registers 5848
Total pins 52 / 240 ( 22 % )
Total virtual pins 0
Total block memory bits 655,360 / 7,024,640 ( 9 % )
Total RAM Blocks 80 / 686 ( 12 % )
Total DSP Blocks 0 / 156 ( 0 % )
Total HSSI RX PCSs 0
Total HSSI PMA RX Deserializers 0
Total HSSI TX PCSs 0
Total HSSI PMA TX Serializers 0
Total PLLs 1 / 7 ( 14 % )
As you can see, there is plenty of room to grow a P1V design on this board.
I hope someone gets a chance to try it out!