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P2 is SoC?
2013-03-15 - 02:33:14
edited 2013-03-20 - 12:07:29
I've just seen posts about the P2 coming with SDRAM and also somebody mentioned Linux...
Makes me wonder... Does P2 count as a System on a Chip (SoC)?
As I read the wiki, I think it might:
2013-03-15 - 03:03:50
edited 2013-03-15 - 03:03:50
Sure, why not?
Depends what you mean by system.
You want UART, video, keyboard, mouse, clock, timers, disk interface (SD card), on a single chip system? Then even the PI is a SoC
Consider that we can put an entire 1970's vintage 8 bit computer emulation on a P1.
2013-03-15 - 03:56:34
edited 2013-03-15 - 03:56:34
Yeah, it's all about context.
When I turn on the P2 emulation and go a few hours with it just running while I send data to it, run things, manage the cores, get data, etc... it sure seems like a little system, particularly now that the display capability is exposed to us. Things are missing though. It's awful primitive to develop right there, though small programs are possible. Really, an external system is needed. Of course the right program loaded at boot would extend that considerably.
In any case, that's a new experience! Seems more "computer" system like to me given that mode of operation. Possible to get data in, out, stop and start multiple programs all while running without reset. For me personally, that's one "system" definition. No reboots or cold starts needed to interact across multiple purposes or sessions.
P1 wasn't really like that without some programming and then things were tight enough to make it more of a curio to me than anything else, though the people running CP/M might just argue otherwise as they could do a lot of the same stuff on a running P1...
So that's one context.
Another might be the whole works is just some ancillary control interface, and then it's more micro controller than system, isn't it?
Seems to me, the same question has been asked a lot over the years too. Put a 6502 or 6809 on a board with a ROM, and what is it? Computer or controller? All about context.
IMHO, the multi-core aspect makes this discussion interesting, and really interesting on P2, because the chip itself has some basic management capability built in now. The engineer can choose to expose that, or not, or maybe just during development, changing the context significantly as far as somebody else is concerned.
Heck, a well written program could feature modular design such that it would be possible to fire up a P2, send over the initial case and watch it run. Engineer sees something they don't like, or perhaps just wants to do something like test a couple of different displays. Well, the usual build, power on, upload, run cycle is always on the table, but that might take a while, depending. On a P2 with it's monitor exposed, the engineer could just kill off the running display core, upload a new display driver and start that core up again, which brings up the other display with the rest of whatever it is running the whole time!
Not sure what to call that, but fun!
2013-03-16 - 18:08:31
edited 2013-03-16 - 18:08:31
Was just reading through the instruction set here:
(Is this up to date?) (I wish Parallax would put a publication date on these things... I see 2011, so I guess it can't be too old)
And another thought crossed my mind.... Is this still RISC?
Seems there are a ton of new instructions.
But, after consulting wikipedia, I guess it is because most of the instructions are single cycle.
Anyway, now I have a bunch of questions about the new instructions... Guess I should search this forum to see if they've already been answered...
2013-03-20 - 12:07:29
edited 2013-03-20 - 12:07:29
I'm sure someone will figure out how to do some really absurd things with the P2!
A big external SDRAM, paged memory, and XMM...