Hydra "xtreme 512k card" sram status

Ok, got the HYDRA sram cards back, built one, worked 100% first try. All the modes seems to work, post inc, dec, latching, etc. Been trying to cause noise problems to see if ever there is a lost bit, none yet. Now, I am going to start running some final high speed tests, and if all works out then start on the documentation and final product stuff and send it to manufacturing for bulk production. While that goes on we will work on some graphics driver demos, but we want to release this asap, so software will not delay release, once the hardware is ready to ship, we will put it for sale.

But, looks good so far, LOTS of LEDs on it [noparse]:)[/noparse] And once again for those not following this, the features are:

- 128K EEPROM on board.
- 512K SRAM.
- 0-64K directly addressable by latching 2 byte address.
- 64-512K addressable by block addressing and pointer incrementing/decrementing in the memory controller.

- Re-Programmable CPLD

Target price $39-49

Cool thing, can be used with anything... just need a 20-pin edge connector 10/10 with .1" spacing and you can plug it in. So you can add it to other propeller or stamp projects as well.

You need 3 (control) + 8· (data) lines to interface.

Andre'
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  • 54 Comments sorted by Votes Date Added
  • edited March 2007 Posts: 0Vote Up0Vote Down
    Can't wait to get my hands on it : D ...

    But 3+8 lines... that means you're using all the I/O lines, both HydraNet lines but where does the third control line come from? SCL? And there prolly isn't a CS line, so a SD card can't be added... as 3 ctrl lines are just enough for R/W, clock and a mode setting/address loading ctrl...

    And can the CPLD be programmed with free tools? Free tools that work with a self-built serial or parallel cable?
  • edited March 2007 Posts: 985Vote Up0Vote Down
    I am using the RX line for the 3rd. And yes, the CPLD can be re-programmed with free tools in ABEL. And I will provide the schematic for the programmer, very simple actually with the parallel port.

    Right now I am running fractal rendering algorithms in the SRAM and scrolling them around to test the memory with something graphical, much easier to "see" bugs that with all the standard tests marching 1's, 0's, patterns, blah, blah. All that works, so now doing lots of graphics in the memory. Then next will be the graphics driver that uses it and see how fast I can push it all. Of course the CPLD goes much faster than the prop, 200-400 Mhz roughly.

    Andre'
  • edited March 2007 Posts: 0Vote Up0Vote Down
    Sorry for sounding ignorent but what is a CLPD?

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    lets see what this does... KA BOOM (note to self do not cross red and black)
  • edited March 2007 Posts: 985Vote Up0Vote Down
    Complex Programmable Logic Device

    Basically, a 2D matrix of "logic blocks" connected together with a switching matrix. Each block usually consists of a flip flip, mux, IO, look up table, and some simple or/and logic.

    You write code in a HDL (Hardware Description language) and this is translated into the target CPLDs architecture and "fit" into it then the resulting "program" is downloaded into the CPLD and this configures it for use.

    The FPGAs are the next size up, "field programmable gate array" which is really a bad name. I think VCPLD would be better, that is, VERY complex programmable logic device.

    hmmm...I think I will patent that!

    Andre'
  • edited March 2007 Posts: 0Vote Up0Vote Down
    Ah, all the time I've thought that the RX/TX pins are connected to the USB end of the FTDI chip, not the serial end (well, that wouldn't have made any sense... since USB needs 4 pins and it'd be of very little use anyway...). So with sharing some pins w/ the EEPROM and SRAM, it might be still possible to add SD support ... Does the card have 0,1" holes for signals like the other cards?

    Oh and by the way, what'd be my chances of breaking the I2C chip on the card if i'd cut the address pin, solder it to +3,3V and cut the loop lines? a) Would it work, ie. would I have 256KB of EEPROM after that b) would I break the I2C chip with heat if I'd try to solder a pin that has been cut?
  • edited March 2007 Posts: 985Vote Up0Vote Down
    The EEPROM is totally seperate, so you can cut lines or remove it if you want. Cutting the loop might prove a little harder since I used a lot of copper, but a knife and a steady hand, no problem. As far as header holes no luck, "but" all of the header pins used are via'd to the other side of the board, so you can squirel wires into them if you want to.

    Andre'
  • edited March 2007 Posts: 0Vote Up0Vote Down
    Okay, thanks Andr
  • edited March 2007 Posts: 985Vote Up0Vote Down
    Also, FYI, the eeproms already do cascade. When you plug in the expansion card, it selects the card eeprom at address 0, then teh board eeprom becomes address 1, so a total of 256K is available.

    Andre'
  • edited March 2007 Posts: 0Vote Up0Vote Down
    Okay... O_O I was nearly gonna ruin my EEPROM card [noparse]:D[/noparse] thank you very much... Yes, I know that it is in the book, I have no idea why I didn't notice it : P
  • edited March 2007 Posts: 985Vote Up0Vote Down
    Also, the blank experimenter card is a good place to start as well. The parallax mini white solderless breadboard fits on it and you can use that plus the header to interace experiments before commiting them to solder.

    Andre'
  • edited March 2007 Posts: 0Vote Up0Vote Down
    Thank you Andrel for the explanation of a CLPD

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    lets see what this does... KA BOOM (note to self do not cross red and black)
  • edited March 2007 Posts: 985Vote Up0Vote Down
    Sure. Also, we are going to release a "Programmable Logic Starter Kit" soon that features a CPLD, built in programmer, tutorials, and all for under $99. Basically, to get people into CPLDs and FPGAs that don't know where to start.

    Andre'
  • edited March 2007 Posts: 0Vote Up0Vote Down
    Sounds good ^_^ And I'm going to prototype on a breadboard anyway, that's what I always do...

    You said that the CPLD can be programmed with ABEL. I've never heard of that language before, why isn't it programmed with Verilog or VHDL? Or can they be used as well?
  • edited March 2007 Posts: 985Vote Up0Vote Down
    verilog/vhdl are higher level and more abstract. Higher abstraction means less control, less control means more assumptions for the silicon compiler, so for smaller CPLDs ABLE or CUPL are preferred. You can look them both up to get an idea of the syntax, but similar to verilog, not as powerful, but much more specific.

    Andre'
  • edited March 2007 Posts: 0Vote Up0Vote Down
    Ok, so Verilog & VHDL usually generate code that's far too inefficient for CPLDs? ... I'll take a look at CUPL and ABEL etc. when I have the card and a programming cable : P

    And is the difference between an FPGA & CPLD only a quantitative one? Or is there a difference between the functionality of logic blocks or routing?
  • edited March 2007 Posts: 0Vote Up0Vote Down
    Whether Verilog/VHDL can be used with CPLDs depends on the number of cells and the project. There is a structural difference between CPLDs and FPGAs, I suggest checking out the specsheets for various devices so you will fully understand. FPGAs in general are much more configurable than CPLDs, it is the extra confurability and less dependance on·optimized layout that enables semi-automated programs such as Verilog to work well. It's relative inability to optimize placement of logic equations in a confined configuration of a CPLD as compared to a human is what makes using a lower level program such as ABEL a better choice.

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    Paul Baker
    Propeller Applications Engineer

    Parallax, Inc.

    Post Edited (Paul Baker (Parallax)) : 3/18/2007 3:50:57 PM GMT
  • edited March 2007 Posts: 0Vote Up0Vote Down
    Wow, thanks for your replies Andr
  • edited March 2007 Posts: 985Vote Up0Vote Down
    People have even written translators from C, python, and other languages to verilog as well, so the main point about HDL programming is just understanding parallel programming, the language is really just syntax that you have to memorize and you spent 99% of your time trying to figure out the syntax of how to say what you want to say.

    Andre'
  • edited March 2007 Posts: 0Vote Up0Vote Down
    What sort of projects are you looking at doing with the "Programmable logic starter kit" andre'?? Anything as complex as a GPU or a very simple CPU? Something that like a GPU that could be used in combination with the Hydra would be very cool
  • edited March 2007 Posts: 985Vote Up0Vote Down
    The kit is targeted to customers that simply have no idea what programable logic is all about, but know they want to play with it. So its like many of the other dev kits out there with CPLDs or FPGAs, but I made it with a specific set of tutorials and projects in mind, so you get the kit, do the tutorails, walks away -- "ah,ha now I see how what its all about, not as bad as I thought!".

    The CPLD on there isn't nearly powerful enough to be a GPU or anything. But, you can definitely generate NTSC or VGA with it, do counters, state machines, all kinds of blinking lights, sounds, etc. And I should how to program it with a tool you can make (comes with it built in of course), so the point is, that literally in 2-3 days of playing with it, you can take a QFP cpld chip solder it on your board and use it.

    The problem with CPLDs and FPGAs there is just a ton of solutions, tools, this that, hard to get started for people, so when I was evaluating this particular technology line, I went to buy the dev kit, it was $400-500! I was like I can do better, so mine will sell for $59-99, and have a programmer built in, and have some documentation other than the tool docs.

    Andre'
  • edited March 2007 Posts: 0Vote Up0Vote Down
    Cheers for the info. This would suit me more than the SRAM card as the only reason I was buying it was the CPLD aspect. Don't suppose you have a lead time Andre'? I know you want to get this project out the door first, but some more info would be nice [noparse]:)[/noparse]
  • edited March 2007 Posts: 985Vote Up0Vote Down
    The CPLD kit is supposed to be sold at the maker faire, so that was a best case time for delivery. So about 1.5 months.

    Andre'
  • edited March 2007 Posts: 985Vote Up0Vote Down
    By the way, here's a pic of what it looks like. The final version will of course be a cool color other than green.

    Andre'
    1200 x 800 - 197K
  • edited March 2007 Posts: 0Vote Up0Vote Down
    that is Xtremely cool [noparse]:)[/noparse] I think the power LED would be nice in blue though, to match the Hydra and to differentiate it from the memread/write and addlatch LEDs.

    Damo
  • edited March 2007 Posts: 985Vote Up0Vote Down
    Blue LEDs in the 603 size seem to need a lot of voltage, I had a blue one, 2 manufactures, and both want well over 3.3V to be bright, so I have to look at that.

    Anyway, testing is going well as is the API, very shortly I will send these out of manufacturing and put the products up, I might even put them up for pre-purchase.

    Andre'
  • edited March 2007 Posts: 985Vote Up0Vote Down
    Ok, looks like the memory is working 100%, I can't seem to get it to perform a single bad operation at warp speed, been running fractal explorer software for days straight 24/7.

    So I will finish up the asm/spin drivers, then I need to make a video driver demo for bitmapped graphics. But, I think I can go ahead and start the manufacturing process. Then we can always add more software later, best to get this done in out there. The drivers can't really take advantage of the SRAM speed, you must code the SRAM access right into your spin or ASM code to get highest perfomance. But, these drivers are good examples of how it works.

    I think I am going to go for a RED pcb, looks pretty slick against the black.

    Also, you can easily put a rechargeable battery connector on this via the CPLD programming port, put a diode inline to allow it to charge up till .2-.3 volts of max and then the SRAM will retain the program, as long as you play with it each day, it should easily hold the data for a long time. So that's another little trick to do like the NES carts with battery backups in them.

    Andre
  • edited March 2007 Posts: 0Vote Up0Vote Down
    Wait, the Hydra is black? : D Why I've not noticed it before o.o'' Even though I've prolly stared hours at the debugled...
  • edited March 2007 Posts: 0Vote Up0Vote Down
    I'm currently working on a project that I want to be able to use this memory card on when its available.
    Can we get a schematic at least showing the exact pinouts needed for interfacing with the card
    and possible a part number for the connector that you are using.

    Also any thoughts on the best way to hook up two propellers to the same ram card simultaneously [noparse]:)[/noparse]

    Thanks,
    Chad
  • edited March 2007 Posts: 0Vote Up0Vote Down
    Will the video driver be for NTSC or VGA? I'm curious.

    I can't wait for this to come out; I'll definetly be buying one. Any timeframe estimates as of yet?
  • edited March 2007 Posts: 985Vote Up0Vote Down
    If I have time to make the video driver it will be NTSC.

    The pinouts that the card uses are the exact same as the interface header, and there is no part # per se, the header is a standard edge connector 2 sided, 10 contacts each side 0.1" spacing. The interface itself was uploaded to this forum, I can't seem to find it (mike, you remember where that link was?), but the interface uses the 8 IO's from the VGA interface, and then it uses the 3.3V power, ground, USB_TX, NET_RX, and NET_TX and that's it.

    Do you want to use the card for a seperate project not plugged into the hydra?

    Andre'
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