New P2 Silicon

cgraceycgracey Posts: 11,511
edited 2019-08-20 - 23:03:11 in Propeller 2
Here is a link to the new instruction sheet for the new silicon:

https://docs.google.com/spreadsheets/d/1_vJk-Ad569UMwgXTKTdfJkHYHpc1rZwxB-DcIiAZNdk/edit?usp=sharing




Here are some current measurements on the old vs. new silicon:
MHz+cogs vs I@1.8V	P2 v1	P2 v2	v2/v1
--------------------------------------------------
20MHz PLL, 1 cog	66 mA	29 mA	44%
20MHz PLL, 2 cogs	69	32	46%
20MHz PLL, 4 cogs	76	37	49%
20MHz PLL, 8 cogs	89	49	55%

40MHz PLL, 1 cog	129	55	43%
40MHz PLL, 2 cogs	136	61	45%
40MHz PLL, 4 cogs	148	72	49%
40MHz PLL, 8 cogs	175	94	54%

80MHz PLL, 1 cog	253	106	42%
80MHz PLL, 2 cogs	266	118	44%
80MHz PLL, 4 cogs	290	141	49%
80MHz PLL, 8 cogs	344	186	54%

160MHz PLL, 1 cog	497	208	42%
160MHz PLL, 2 cogs	521	231	44%
160MHz PLL, 4 cogs	570	275	48%
160MHz PLL, 8 cogs	672	365	54%

320MHz PLL, 1 cog	962	407	42%
320MHz PLL, 2 cogs	1010	455	45%
320MHz PLL, 4 cogs	1104	541	49%
320MHz PLL, 8 cogs	1295	718	55%

The new silicon takes about half the power.

Here's the code that was running in the P2's:
'
' Set PLL
'
dat		org

		hubset	##%1_000000_0000001111_1111_01_00	'alter
		waitx	##20_000_000/100
		hubset	##%1_000000_0000001111_1111_01_11	'alter
'
' Launch n+1 cogs
'
.loop		coginit	n,#@pgm		'launch cogs 7..0
		djnf	n,#.loop	'last iteration relaunches cog 0

n		long	7		'set to 0, 1, 3, or 7
'
' Program that runs in each cog
'
		org

pgm		cogid	x
		add	x,#56

.loop		drvnot	x
		jmp	#.loop


x		res	1

I don't know how fast the new silicon can run because it keeps up with the PLL as it max's out around 390MHz at room temperature. I hit it with freeze spray and the frequency climbed to 435MHz! I couldn't get it any colder than that.
«13456713

Comments

  • No way ... That is beyond crazy ... You're the man Chip.

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  • Even running at 390MHz, the chip is barely warm to the touch.
  • jmgjmg Posts: 13,784
    cgracey wrote: »
    Here are some current measurements on the old vs. new silicon:
    How is that measured ? Is that Current at 1.800V, and what is the current meter resistance ?
    cgracey wrote: »
    The new silicon takes about half the power.
    Looks like the clock gating was worth the effort ;)
    Better numbers mean some P2 applications could use simpler LDOs.
    cgracey wrote: »
    I don't know how fast the new silicon can run because it keeps up with the PLL as it max's out around 390MHz at room temperature. I hit it with freeze spray and the frequency climbed to 435MHz! I couldn't get it any colder than that.
    So looks promising for hitting 250MHz for HDMI ?

    That's just testing a loop ?
    How does Cordic and more complex parts MAX out ?
    What about the 64b CNT, does that run to PLL_MAX too ?
    How many P2-ES2 samples can you test ?
  • 390Mhz with no cooling?!? that's impressive well done Chip! and 50% power savings on top of that? double well done!
  • jmgjmg Posts: 13,784
    cgracey wrote: »
    ... I hit it with freeze spray and the frequency climbed to 435MHz! I couldn't get it any colder than that.
    I saw this go past today... could be just the thing for those of the over-clocking fringe ? ;)

    MP8833 (prelim) 1.5A Thermoelectric Cooler Controller


  • I used a digital power supply with a current meter to deliver the current at 1.8V to the load. I used a voltage meter at the load to adjust the power supply output voltage upwards, as needed, to maintain 1.8V at the load. I took current readings from the digital bench power supply.
  • cgraceycgracey Posts: 11,511
    edited 2019-08-01 - 10:13:57
    Because of the way the timing paths are optimized, as needed, they are all up against the same wall. When the chip fails from a too-short clock cycle, thousands of paths fail at the same time. So, it's not like one part of the chip can run faster than any other part. This is nice, because you can back off from the failure point and be confident that things are going to be okay.
  • Stunning results, Chip. That clock gating has really helped
  • Tubular wrote: »
    Stunning results, Chip. That clock gating has really helped

    Yeah, it was just a switch that Wendy enabled in the synthesis tool. It actually caused a net reduction of logic, since there were many flops which mux'd their outputs back into their inputs to realize an "ENA" signal. Those circuits were more numerous than the clock gates, and they almost all went away.
  • Cool! Pardon the pun! :cool:
    Congrats! Well done Chip!
    Hey Tubular, it's dry ice time again. :)
    Melbourne, Australia
  • Way cool outcome there Chip!

    I'm thinking most, if not all, of the speed gain is due to the lower die temperature from less heating, ie: Lower wattage produces a shallower gradient.

    "... peers into the actual workings of a quantum jump for the first time. The results
    reveal a surprising finding that contradicts Danish physicist Niels Bohr's established view
    —the jumps are neither abrupt nor as random as previously thought."
  • Your spinning Fozzie test code (now in colour?), half an eskie of dry ice, and half a gig of clocks

  • evanh wrote: »
    Way cool outcome there Chip!

    I'm thinking most, if not all, of the speed gain is due to the lower die temperature from less heating, ie: Lower wattage produces a shallower gradient.

    I think so, too.
  • Tubular wrote: »
    Your spinning Fozzie test code (now in colour?), half an eskie of dry ice, and half a gig of clocks

    If you could get a clock generator to drive 400MHz+ into XI, you could find the limit. As it is, the logic is always faster than the PLL.
  • cgracey wrote: »
    Tubular wrote: »
    Your spinning Fozzie test code (now in colour?), half an eskie of dry ice, and half a gig of clocks

    If you could get a clock generator to drive 400MHz+ into XI, you could find the limit. As it is, the logic is always faster than the PLL.

    Looks encouraging Chip.
    We got to 372MHz on V1 blob top with dry ice.
    Melbourne, Australia
  • ozpropdev wrote: »
    We got to 372MHz on V1 blob top with dry ice.
    Huh, it must depend on what is running, I've been going that high at room temperature https://forums.parallax.com/discussion/comment/1472679/#Comment_1472679

    It didn't last without cooling though.

    "... peers into the actual workings of a quantum jump for the first time. The results
    reveal a surprising finding that contradicts Danish physicist Niels Bohr's established view
    —the jumps are neither abrupt nor as random as previously thought."
  • cgracey wrote: »
    If you could get a clock generator to drive 400MHz+ into XI, you could find the limit. As it is, the logic is always faster than the PLL.
    I thought the PLL could go above 400 MHz on the v1 chip with DIVP = 2, ie: The PLL wasn't the limiting factor. And you've modified it in the v2 chip to go a little higher still, right?
    "... peers into the actual workings of a quantum jump for the first time. The results
    reveal a surprising finding that contradicts Danish physicist Niels Bohr's established view
    —the jumps are neither abrupt nor as random as previously thought."
  • Congratulations, Chip! When are the chips with the production packages due to come in?
  • This is a fantastic result for the reduction in current required now Chip.
  • Just tested my v1 at 25°C room temp with DIVP=2 and got up to 208 MHz sysclock (416 MHz PLL).
    Warmed up to 85°C, worked to 190 MHz sysclock (380 MHz PLL).
    "... peers into the actual workings of a quantum jump for the first time. The results
    reveal a surprising finding that contradicts Danish physicist Niels Bohr's established view
    —the jumps are neither abrupt nor as random as previously thought."
  • Outstanding sir! So glad to see it work as well as predicted!

    Any idea of what the phase noise is like on the PLL?

    Again, congrats Chip! We all appreciate your hard work and vision of the P2.
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  • you have a good one there, evanh. Its a keeper...

    My memory is we needed to use the dry ice to get the thing up and running (ie boot 8 cogs). Once up and running, it was mostly happy to continue on its way

    We were also testing using P2D2's, which would be a little bit more thermally constrained
  • evanhevanh Posts: 7,522
    edited 2019-08-01 - 13:00:31
    I'm not stressing the power, only one cog running.

    There's not a great amount of headroom but point is the PLL is not the limiting factor when DIVP=1. And I'm pretty sure Chip has tweaked the PLL performance in the v2 chip for the PLL to go even faster there.
    "... peers into the actual workings of a quantum jump for the first time. The results
    reveal a surprising finding that contradicts Danish physicist Niels Bohr's established view
    —the jumps are neither abrupt nor as random as previously thought."
  • Fabulous result Chip. Congratulations!!!

    The increased speed and massive power reduction is going to open up some interesting uses :)

    With this clock speed it’s a shame we can’t throttle some of the cogs to half the speed of others. I know, there would be other hardware ramifications, but you cannot stop me from dreaming.

    Now what is that 90nm P3 going to run at ;)
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  • koehlerkoehler Posts: 576
    edited 2019-08-01 - 15:30:59
    cgracey wrote: »
    Here are some current measurements on the old vs. new silicon:

    I don't know how fast the new silicon can run because it keeps up with the PLL as it max's out around 390MHz at room temperature. I hit it with freeze spray and the frequency climbed to 435MHz! I couldn't get it any colder than that.

    I think Parallax should take a note out of CPU Proc Manf's playbook and get some LN2/cooler thing experiment going.
    Just a small amount of $$ might make a nice ripple in the HaD/Maker-verse...

    Heck, if Chip doesn't have the time, maybe forward a golden sample to someone on here who has the interest/skills to do it for you?
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  • Aside from all the fluff, is the quad decode working....and what are the spec's?
    Failure is not an option...it's bundled with the software.
  • Congratulations Chip !!

    BTW) 350MHz is about the "reliable" limitation of the TSMC 180nm process. Your mileage may vary. When I built a Gigabit Ethernet chip for National Semiconductor, we used the same TSMC 180nm process. To achieve speeds of 1 Gig there were four clocks running at 250MHz with each of them locked to one another through a specific phase delay.


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  • Great news! Everyone at Parallax must be very relieved and happy.
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  • So close to SVGA hdmi, though who have 4:3 monitors still around?

    Name 800x600p60
    Aspect Ratio 4:3
    Pixel Clock 40.000 MHz
    TMDS Clock 400.000 MHz

  • tonyp12 wrote: »
    hough who have 4:3 monitors still around?

    Well, few people really, which is why you can get 4:3 and 5:4 monitors of average quality fairly cheap. Altough those often don't have DVI / HDMI anyways.

    Would 1080i work though?

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