Switching from RCFAST (~ 23MHz) to Xtal (20.000MHz) is tested, and the Xtal Cap settings also tested
Xtal: TSX-3225 20.0000MF20G-AC3 EPSON CRYSTAL 20.0000MHZ 9PF SMD 20MHz ±20ppm ±10ppm 9pF 60 Ohms
HUBSET ##%0000_000E_DDDD_DDMM_MMMM_MMMM_PPPP_CCSS 'set clock mode
CC Xtal pins mode
SS Osc Select : RCFAST : RCSLOW : XI : PLL
%CC XI status XO status XI/XO Z XI/XO caps Measures ppm change
%00 ignored float Hi-Z OFF
%01 input 600-ohm drive 1M-ohm OFF -> 1000.1439Hz +144 ppm
%10 input 600-ohm drive 1M-ohm 15pF per pin -> 999.9933Hz -6.700 ppm << operating point.
%11 input 600-ohm drive 1M-ohm 30pF per pin -> 999.9472Hz -53 ppm
%SS Clock Source Notes
%11 PLL CC != %00 and E=1, allow 10ms for crystal+PLL to stabilize before switching to PLL
%10 XI CC != %00, allow 5ms for crystal to stabilize before switching to XI
%01 ~20kHz ~20kHz, can be switched to at any time, low-power
%00 20MHz+ 20MHz+, can be switched to at any time, used on boot-up.
Taqoz test script, to Enable PWM, then switch clock sources (after this a reset is needed to recover TAQOZ & autobaud).
Tests confirm switching without any delay is not reliable.
it may be that before the Xtal amplitude is large enough, that noise/illegal clock widths can come from Xtal Osc.
// Reset target '> '[esc] enables TAQOZ
// wait appx 250ms needed, for TAQOZ to load
'16 PIN 200 10000 1 PWM',$0D
// wait ~5ms for ok echo,
// Then Enable Xtal Osc, VAR delay for Osc Start, and switch to Xtal source.
'%11_00 HUBSET 62,000 WAITX %11_10 HUBSET',$0D
Scope image shows the boundary/marginal case, were the starting delay is too small (2.7ms here at 62,000) and the Xtal has not fully started - there is visible a longer delay, as the clock source handover occurs.
When the WAITX is sufficiently large, there is no extra delay, as the switch over is done in 1 SysCLK.
Xtal oscillates in all 3 Cap modes, even minimum C, and the %10 mode has < 10ppm error.
TAQOZ PWM has a couple of issues :
a) It generates a wide initial pulse, before the user pulses appear after ~ 6ms
b) It seems to be off-by-2, ie the output numbers, are half the sysCLK - is that a Smart Pin bug, or a TAQOZ bug ?]
... Ahh, buried far away from the PWM examples, is mention of SAW, (no examples) & some trials reveals
'16 PIN 200 10000 1 SAW',$0D
removes the unexpected 2x error & also changes the pulse hiccups.
In SAW mode, the 2.6ms HI is still present, but there is much less delay in the pulse train repeats, after the falling edge. Prr of 433us has first low of 442us
Looks like the TAQOZ docs need some corrections & clarifications on actual SysCLK cycle counts and modes.
Changed to 160MHz to look for jitter, and also measured ppm temperature effects
160MHz is SAWtooth /10k of
1-16k/15999.836 = -10.250ppm
Then change to 20MHz Xtal, and measure over next 5 mins
1-1k/999.9900 = -10.000ppm
1-1k/999.9908 = -9.200ppm
1-1k/999.9913 = -8.700ppm
1-1k/999.9922 = -7.800ppm ....cooling down,