With the present thermal envelope on P2, knowing the die temperature is likely to be more important.
One possible pathway, is to use the TEST pin substrate/esd diode driven negative with a light current, and use that on-die diode as an indicator of temperature.
Q: To check if this is even feasible, can someone with a P2 device isolate TEST, and use a multimeter (diode range) to measure the -ve dirn diode drop (-0.6v), and then run various CLK speeds to change the die temperature ?
If that works, a part like onSemi's MAX1720 (SOT26+passives) can be used current fed/voltage starved to drive the diode ~ -100uA.
Then either MAX1720 V+ can be measured (should ~mirror -Vd) or the -Vd can feed to a Analog pin, via a resistor scaled to give ~ 0V at cold temps.
The on-chip resistor tolerance will matter here, as it forms a divider with the external resistor.
A benefit of the resistor ( >>10k) is it could connect to a non-boot-sensed SPI pin, to get a no-added-pin cost thermal sense path.
Other ideas :
Possible could be a part like NCT75MNR2G (OnSemi, i2c TempSense, 2x2mm0.5 ~ 26c) - but that needs i2c connections, and is not an on-die sense element.
They also have N34TS04, bumps to ~ 80c, but adds a 4kb EEPROM in a 2x3 package.
Or, use more of the Smart Pins, (10uA source, 100uA sink) & capacitor couple to TEST with a ~22~50k pulldown & use the cap as a voltage level shift
Example numbers here give
10uA Source C charge times (initial power up) - after power up, keep charge balance time > (10x Measure time). Vpin ~ +220mV during charge = LOW logic.
0.1uF 0.1u*3.3/10u = 33ms
0.33uF 0.33u*3.3/10u = 109ms
100uA sink C Measure time (100mV dV indicator) Analog voltage is initially Vio-Vd (Pulldown steals 27~12uA of the 100uA test drive)
0.1uF 0.1u*0.1/100u = 100us (Tcharge >> 1ms)
0.33uF 0.33u*0.1/100u = 330us (Tcharge >> 3.3ms)
Measure cost here is just 2 passives, but it does need a dedicated pin for P2-Temp reading.
If that does work, it makes a good skewed-current-drive use demonstration.
or, if the Resistor/Current source have stable & consistent enough tempco's, yet another smart-pin approach would be to use any/best mix of the termination choices of
1.5k/15k/150k & 1mA/100uA/10uA which I think are available going both ways (Hi & lo). That could apply to a SPI pin ?