P2 documentation

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  • jmgjmg Posts: 12,064
    T Chap wrote: »
    Maybe move these OT threads to my PCB thread.

    Yes, artwork design is a separate topic, but the pinout docs do need to make it clear there is a GND PAD, and thumbnail ? illustrate how large it is.
    Chip probably has a real package image, full drawing, and maybe even some samples ?
  • Peter JakackiPeter Jakacki Posts: 7,714
    edited June 5 Vote Up0Vote Down
    The size of the centre pad and such like along with the proper name and other dimensions are all to be found on page 3 under mechanicals, that is, not the pinout, not the diagram, not representations, the actual mechanical dimensions. So all the information is there in its various forms in their relevant sections. Since the ground pad is already illustrated in the mechanical section no attempt was made to mess up the chip pinout drawing although the corner "pad" may be replaced with a simple arrow. Sometimes you just have to try different things and let them sit to see how they breathe.

    Don't forget to refresh your page when viewing as this is updated every day almost.

    Btw, i will be adding a recommended pcb footprint section. With thermal pads it's normal to use very tiny thermal vias.

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  • I missed that drawing. Thanks! There’s a lot of room outside the pad.
  • jmgjmg Posts: 12,064
    The size of the centre pad and such like along with the proper name and other dimensions are all to be found on page 3 under mechanicals, that is, not the pinout, not the diagram, not representations, the actual mechanical dimensions. So all the information is there in its various forms in their relevant sections. Since the ground pad is already illustrated in the mechanical section no attempt was made to mess up the chip pinout drawing although the corner "pad" may be replaced with a simple arrow. Sometimes you just have to try different things and let them sit to see how they breathe.
    I think on the physical pinout page, the corner ground is certainly distracting (TQFP100 meets SOT223?) , and it needs a 'show both sides' image at the actual size area.
    Many of the possible users will not have seen Exposed PAD Packages before, but their newer Ardunio likely has a QFP package on it.
  • @jmg - I'm aware of little details like that but this is a top view and that little ground pad detail was simply added to show that there was a ground connection even though the mechanical drawings clearly show the real pad. As i have already said, i may just use an arrow but i am not going to mess up a top view. Part of the reason is to do with visuals because it is a shortform combining the attributes of a brochure and a datasheet where we want the front page to say it all, a bit like a movie poster

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  • Cluso99Cluso99 Posts: 13,909
    edited June 6 Vote Up0Vote Down
    Under SmartPins...
    2/3/5/8-bit-unanimous input filtering with selectable sample rate

    *5 – Connect all VIO pins to I/O supply voltage
    VIO powers an adjacent set of pins. Each set can have different voltages. What is the range??? 1V8 or 2V5 to 3V3?

    BTW Fantastic job Peter!
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  • Peter JakackiPeter Jakacki Posts: 7,714
    edited June 6 Vote Up0Vote Down
    Yes, it seemed safer for the moment to say "connect all the pins" then to go into what the manual would discuss at length. Chip said they weren't designed for 1.8V but I suspect that 2.5V should be ok within lower drive limits.

    As for the smartpins I just copy and paste that stuff but you can read more in the P2 doco under "Configuring the Digital Filters for SmartPins" section as it uses this wording "and must be unanimously high or low to change the filter output to high or low".

    The shortform should give us all something we can print out on a glossy but you have to download the pdf for better print quality. All the doc files and images are in the P2/doc folder.

    BTW, this is the current view of the first page so always refresh the cloud document if you left it open. Another page is dedicated to the pinout table, the next for mechanicals and some links and then another optional page with some information about the tools.
    @Cluso99 - you need to do up a Google doc or at least dropbox a document/pdf for your boot software. Start with the basics, then build on it.
    p2shortform.png


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  • IIRC, sometime ago, Chip has said the smart pins were designed, focusing a 3.0 <= Vio <= 3.6 VDC range.

    I suppose that not only the drive limits would change, when used into their digital realm, under such lower power suply specs.

    Chances are they'll display some very different characteristics (transition delays), suposing they could be fully operational, at all, in the event their operating voltage is shifted to the 2.25 <= Vio <= 2.75 VDC range. Worse values (delays) could be expected at lower voltages, again, if fully operational, at all.

    I can say nothing about them, if and how they'll behave, when used as DACs (analog realm).
  • cgraceycgracey Posts: 9,541
    edited June 6 Vote Up0Vote Down
    Yanomani wrote: »
    IIRC, sometime ago, Chip has said the smart pins were designed, focusing a 3.0 <= Vio <= 3.6 VDC range.

    I suppose that not only the drive limits would change, when used into their digital realm, under such lower power suply specs.

    Chances are they'll display some very different characteristics (transition delays), suposing they could be fully operational, at all, in the event their operating voltage is shifted to the 2.25 <= Vio <= 2.75 VDC range. Worse values (delays) could be expected at lower voltages, again, if fully operational, at all.

    I can say nothing about them, if and how they'll behave, when used as DACs (analog realm).

    Yes, running them below 3.3V would cause huge propagation delays and the analog circuits would hardly work. They will be spec'd at 3.3V +/-10%.
  • cgracey wrote: »
    Yes, running them below 3.3V would cause huge propagation delays and the analog circuits would hardly work. They will be spec'd at 3.3V +/-10%.

    Great, just the information we need for the datasheet too!


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  • Peter JakackiPeter Jakacki Posts: 7,714
    edited June 6 Vote Up0Vote Down
    I wanted to get as much information onto the second page as possible so I combined the chip view pinout with the pinout table. Even though I haven't finished it yet, this is a preview of how the shortform can cram a lot into a single double-sided page.
    I want to include "Fritzing" diagrams for boot devices using the P2 chip view on the third page along with the mechanical drawings.
    P2PINS.png
    2404 x 1698 - 701K

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  • Hi Peter
    V2527 should be V2427
    V3225 should be V3235

    keep going, its looking great

  • Tubular wrote: »
    Hi Peter
    V2527 should be V2427
    V3225 should be V3235

    keep going, its looking great

    Thanks Tubular!

    I have just updated it to the latest layout and added basic connections schematic to page 3 as well. I will probably devote more pages to a complete reference schematic and pcb layout including thermal vias and recommended pcb pad sizes etc.

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  • Hi Peter,

    Per your schematic, the ROM and the SD can be used at the same time, no issues at all? That confuses me a bit, because I thought that the SCLK and SDATA pins were swapped (used swapped GPIOs).

    Also, other versions of the Propeller P2 MCU are to be expected, right?

    Kind regards, Samuel Lourenço
  • Is there a known minimum current for the 1.8v regulator? 3.3v?
  • cgraceycgracey Posts: 9,541
    edited June 6 Vote Up0Vote Down
    T Chap wrote: »
    Is there a known minimum current for the 1.8v regulator? 3.3v?

    Today, ON Semiconductor will be running some simulations where all cogs are operating, toggling smart pins, and reading hub memory. This should give us an idea of how much current will be required at 1.8 volts.
  • jmgjmg Posts: 12,064
    samuell wrote: »
    Per your schematic, the ROM and the SD can be used at the same time, no issues at all? That confuses me a bit, because I thought that the SCLK and SDATA pins were swapped (used swapped GPIOs).
    The ROM is inside the chip, so has no minimal test-at-boot effect on the pins. Did you mean to ask : can SPI Flash and SD can be used at the same time ?

  • jmgjmg Posts: 12,064
    I will probably devote more pages to a complete reference schematic and pcb layout including thermal vias and recommended pcb pad sizes etc.
    Good idea.
    A minimal SCH for 'get it working' showing decoupling and supply currents and crystal details.
    eg for crystal, show
    * Does it need external bias R, External CAPS ?
    * What Pin powers the XTAL amplifier
    * What upper MHz limit on Xtal-Osc, and upper MHz on EXTCLK (usually EXTCLK is much higher))
    * What is the connection and drive requirements for external clock (usually XI ?) XO=nc ?
    * What logic levels (1.8 or 3.3) needed, and can it AC couple from a clipped sine TCXO (0.8v p-p) - up to what MHz ?
    * Are there any PLL/divider-imposed limits on EXTCLK ?
    * Include the PLL formula and limits on VCO and PFD
  • YanomaniYanomani Posts: 635
    edited June 6 Vote Up0Vote Down
    As for the GND/thermal vias, to be used as the connection path between the exposed metal pad and any circuit board P2 will be soldered, there was at least a sequence of posts, starting from the following, from evanh, about one year ago.

    Jesus! Time has passed so fast...

    https://forums.parallax.com/discussion/comment/1412469/#Comment_1412469

    I bet this problem was re-visited many other times, before and after, so it's a matter of searching to find more references.

    I realy don't know Chip's actual viewn about this subject, but sure, better peer over the shoulders of those who have already done so, to see how the problem has been conveniently solved.

    Also, as technology advances and geometry node shrinks, it'll be not that commom to find a such large exposed pad to be soldered, like the one P2 sports.

    Then, expect some concerns about circuit board flatness and its flexural rigidity, beyound the basic geometry-related ones, e.g., avoiding any solder flow from the side where P2 is soldered, towards the other side of the board, thru the vias underneath the exposed pad.
  • cgracey wrote: »
    T Chap wrote: »
    Is there a known minimum current for the 1.8v regulator? 3.3v?

    Today, ON Semiconductor will be running some simulations where all cogs are operating, toggling smart pins, and reading hub memory. This should give us an idea of how much current will be required at 1.8 volts.

    Young novice here who knows very little (nothing?) about chip design...
    wouldn't it be a better test if the smart pins were doing something like sending data via UART and the cogs were doing something like calculating random numbers to put into the UART buffers (assuming there are buffers that the smart pins read from)? I'm just thinking, toggling pins probably doesn't use most of the transistors in the ALUs and I'll bet it doesn't use most of the registers and other transistors for the smart pins either. Is this just a preliminary test (because of course it would be very simple to write) and another more in-depth test like i describe will be performed later?
    David
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  • Peter JakackiPeter Jakacki Posts: 7,714
    edited June 7 Vote Up0Vote Down
    @DavidZemon - simple simple tests should always come first because it you can't get them right, then what confidence can you have in more complicated tests? That is, if you can get them to work that is.

    Everybody - you may have noticed how I have taken liberties with graphics and wording and terminology in this unofficial data brief. For instance I may describe the P2 as a "realtime signal processor" rather than a more mundane and underwhelming "microcontroller", the latter which evokes images of 8051 to me. Constructive feedback is welcome because if we do it right it will help to promote the P2 by focusing attention on why this chip is different and better (and more fun). This is also something that Parallax might decide to incorporate into their official documentation eventually. At the very least it will give them some ideas.

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  • jmg wrote: »
    samuell wrote: »
    Per your schematic, the ROM and the SD can be used at the same time, no issues at all? That confuses me a bit, because I thought that the SCLK and SDATA pins were swapped (used swapped GPIOs).
    The ROM is inside the chip, so has no minimal test-at-boot effect on the pins. Did you mean to ask : can SPI Flash and SD can be used at the same time ?
    I did it again! Yes, I wanted to ask exactly that. So, can SPI flash and SD be used at the same time? Thanks, jmg, for the heads up.

    Kind regards, Samuel Lourenço
  • Peter JakackiPeter Jakacki Posts: 7,714
    edited June 7 Vote Up0Vote Down
    @samuell - No and yes. The SPI Flash and SD cannot be used at the "same time" but the SPI and SD can coexist and share the same 4 I/O pins. So you cannot have one cog accessing SD and another accessing SPI at the same time but you can access SD such as read in sectors of a file, and then you can access SPI. Remember that both these devices are serial block devices in that you need to setup the I/O, send a command packet, and then read or write a data block. TAQOZ changes between the two devices transparently, here's a simple one line example of loading 64kB of Flash at address 0 from an open file.
    TAQOZ# 0 SFER64  0 $10000 ADO   I SDC@ I SFC!    LOOP  ok
    

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  • Thanks, Peter.

    In my view, they don't have to be accessed at the same time, so to speak. But if they can coexist, that's excellent for me. My reasoning behind my question was because I thought that the flash memory could be "messed up" while receiving communication for the SD and vice versa. I was afraid that the SPI signals could end up mangled (because one's CS is the others SCLK and vice versa).

    If I wish to boot from the SD card instead of using the flash, can I do it just by inserting the SD card (that will pull-up the appropriate line, as I understood)?

    Kind regards, Samuel Lourenço
  • @DavidZemon - simple simple tests should always come first because it you can't get them right, then what confidence can you have in more complicated tests? That is, if you can get them to work that is.

    Everybody - you may have noticed how I have taken liberties with graphics and wording and terminology in this unofficial data brief. For instance I may describe the P2 as a "realtime signal processor" rather than a more mundane and underwhelming "microcontroller", the latter which evokes images of 8051 to me. Constructive feedback is welcome because if we do it right it will help to promote the P2 by focusing attention on why this chip is different and better (and more fun). This is also something that Parallax might decide to incorporate into their official documentation eventually. At the very least it will give them some ideas.

    What about the controller applications at which it should excel? Signal processor makes me think of those devices that are very optimized for crunching numbers and streaming data for things like real time filtering of signals and such, often trading efficiency at that task for efficiency at more generalized computing or controlling functions. I do however see your point that the P2 is a unique device and that there should be a way to describe it that highlights that. Pehraps just "Octacore Realtime Processor"
    Particularly patient proactive practice positively predicates practically precise poly-processor Parallax Propeller programming paradigms.

    .
  • Ahhh, at last, some feedback on content! :)

    This is what I'm looking forward to discussing, how we describe this unique architecture. For instance, i used the term "signal processor" as i wanted to emphasize I/O without saying that, since that might imply simple bit banging, and i didn't want to use the terms digital signal processing or mixed signal processing since those terms are already used and the understanding is different from what P2 is. But the real emphasis is on "realtime" signal processing IMO. If anyone can think of applications that could help to "describe" what P2 is, then please let me know.

    Instead of Octa core or Octa-core I've simply said OctaCore to also emphasize multiple cores which we know as cogs, but I'm not sure of a term we can use to describe SmartPins without having to describe them, hence the diagram that I hope helps. This reminds me that I had intended to do a detailed diagram of a smartpin, although that is no easy task!

    Thanks for the feedback.

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  • jmgjmg Posts: 12,064
    If anyone can think of applications that could help to "describe" what P2 is, then please let me know.
    Chip's power sim test code is already a good one. FWIR That has 60~62? smart pins generating PWM, and all COGs running. 60++ PWMs will gets people attention.

    I like the idea of examples that run a single smart pin, one for each mode, and another closely related example that launches all practical smart pins.

    I think 30 Duplex Uarts are possible ?

    30 Reciprocal counters should also be possible ? (suddenly that GPS TXCO module is useful..)

    30 high precision, true duty cycle captures should also be possible ?

  • Ken GraceyKen Gracey Posts: 6,285
    edited June 22 Vote Up0Vote Down
    As you discuss documentation and terminology, you'll be coining words that stick with the Propeller. These words can help adoption if they are familiar (self-descriptive and self explanator, for example) or hinder it if they are Parallax-specific.

    Smart pin is intriguing and somewhat self-explanatory. It begs the question about I/O pin features.

    But there's a term I'd love to see us drop: cogs, and replace it with processor. Try using the two terms on a Propeller noob and see how they respond. Next to eight "processors" I'd choose "corse" but "cogs" would be the last one.

    I might be fighting my own little battle in this way, but I think it's an important one.

    Ken Gracey
  • jmgjmg Posts: 12,064
    Ken Gracey wrote: »
    As you discuss documentation and terminology, you'll be coining words that stick with the Propeller. These words can help adoption if they are familiar (self-descriptive and self explanator, for example) or hinder it if they are Parallax-specific.

    Smart pin is intriguing and somewhat self-explanatory. It begs the question about I/O pin features.

    But there's a term I'd love to see us drop: cogs, and replace it with processor. Try using the two terms on a Propeller noob and see how they respond. Next to eight "processors" I'd choose "corse" but "cogs" would be the last one.

    I might be fighting my own little battle in this way, but I think it's an important one.
    (I think you meant 'cores' ?)

    I'd agree - across industry, 'processor' and 'core' are a widely understood words.
    Some care may be needed to separate Microcontroller from Microprocessor - ie P2 is a Microcontroller.


  • @jmg: yes, I meant cores.

    In keeping with your suggestion, perhaps P2 has eight "microcontroller cores" or the more terse term "cores" could be used after the first appearance of "microcontroller cores" in documentation.

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