Custom Layout Mods

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  • jmg wrote: »
    cgracey wrote: »
    ...

    Meanwhile, I rented an ESD zapper gun, since my old one went kaput, and I've been zapping the prior test chip. It has the same ESD circuits as the new one, so it can reveal any ESD weakness in our design. Surprisingly, the chip failed ESD testing miserably! The problem is that the core ground (GND) and I/O ground (GIO), while normally at the same potential, can get a huge differential during a zap.

    The core ground and I/O grounds are not shorted together on the die, but are both bonded down to the exposed pad, which becomes BOTH grounds. This was done to keep core ground currents, which are quite high on the die and cause ~25mV differences on what should be the same "ground", isolated from the I/O grounds which may be doing ADC and DAC operations that would be really compromised by ground noise. Anyway, during an ESD zap, those core and I/O grounds could be 50V apart for a few nanoseconds. This was causing my level shifters to blow out, as delicate NMOS gates were exposed to this havoc.

    In order to fix this, I need to add a resistor and a small ESD clamp on each of the cross-domain connections where the NMOS transistors are being driven.

    I had plenty of ESD protection where I thought it was needed, but totally missed the other vulnerabilities. Today I'm working on the schematic for the PAD ring elements to fix all this.

    That sounds like it will slow signals down ? (and may not give best protection)

    Can you not add some 'fat' back to back diodes (one may be there already) between the two grounds ?
    In normal operation, they are mV separate, but in ESD event, the diodes ensure the GNDs cannot wander too far apart ?


    Yes, I'd like to get away with just big back-to-back diodes. I'm looking through the PDK now to see how to call this out.

    If we could keep the grounds close together, there shouldn't be a need for the resistor-clamp ESD circuits between ground domains. Those circuits do add about 500ps of delay.
  • Assuming this shuttle run goes better than the P2 Hot one did, even if it's not perfect what are the chances some of us might snag one of the beta chips for a little testing of our own? I would be willing to lay out a bit of coin just for the coolness factor of having one of the functional prototypes.
  • This shuttle doesn't have any cogs as such. It basically the ring frame without smarts, word to io pins for testing.
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • cgraceycgracey Posts: 10,151
    edited February 8 Vote Up0Vote Down
    I've been in Colorado Springs all week at Treehouse Design. We are wrapping up the layout changes for the Prop2 pad ring. Things are really coming together.

    Here is a picture of the lady who's been doing most of the work. Her name is Judy and she is really on top of things.

    Judy's husband Mike works here, too. He's laying out the new ESD clamping diodes and now-simplified output transistors. Today we had a few calls with a really good engineer at OnSemi who helped us straighten out some errors we were having. Tomorrow morning, the ESD clamps should come together nicely.

    Meanwhile, Judy is here at 9pm going through the pads and bringing the signals out to the core, and generally tidying everything up. We also increased the top metal layer to 3.0 micrometer thickness from 0.8. This entails some other edits. Everything is shaping up really well.
    2048 x 1152 - 1M
  • idbruceidbruce Posts: 5,675
    edited February 8 Vote Up0Vote Down
    Chip

    It almost sounds like the new CNC just might be running on a P2. However I will still need a development board.

    I wonder who will finish first... I will be welding up the frame very shortly... and my stepper power supplies should arrive Friday.

    Either way, it appears we are both making nice progress.


    Novel Solutions - http://www.novelsolutionsonline.com/ - Machinery Design • - • Product Development
    "Necessity is the mother of invention." - Author unknown.

  • cgraceycgracey Posts: 10,151
    edited February 8 Vote Up0Vote Down
    idbruce wrote: »
    Chip

    It almost sounds like the new CNC just might be running on a P2. However I will still need a development board.

    I wonder who will finish first... I will be welding up the frame very shortly... and my stepper power supplies should arrive Friday.

    Either way, it appears we are both making nice progress.

    That's excellent!

    Maybe you will be done first, though.

    Things on Prop 2 really are moving forward.
  • I'm "just" a forum member, but hats off to Judy and Mike for putting in the long hours to help with Chip's chip. Hope that Judy can sleep late tomorrow and come in around lunch time. It's great that you folks were able to arrange a phone meeting with OnSemi (the right help at the right time, it sounds like). Now, that nearly quadruple increase in the thickness of the top metal layer sounds interesting. Wonder what the story is behind that (and whether Chip will still be able to "peer" through it with his special second-hand machine). Anyway, sounds like great progress is being made. Thanks for the "Colorado update" with the picture of Judy happily slaving away, Chip.
  • Chip

    As much as I enjoy your endeavors, I am sure you would enjoy mine, but I do not provide information to the public about my projects like you do. My current project is a serious one and I will be filing a patent. I know that you are not a big fan of patents, but I am. Either way, I would love to hear your input on my current endeavor and how the P2 could benefit this machine. I am hoping to meet you someday, where Electronical meets Mechanical.


    Novel Solutions - http://www.novelsolutionsonline.com/ - Machinery Design • - • Product Development
    "Necessity is the mother of invention." - Author unknown.

  • Way to go Chip (and Treehouse friends)! :cool:
    Melbourne, Australia
  • cgracey wrote: »
    I've been in Colorado Springs all week at Treehouse Design. We are wrapping up the layout changes for the Prop2 pad ring. Things are really coming together.

    It's interesting, and satisfying, to see a project you've been working on for a long time suddenly start coming together like that. Enjoy.

    Sandy

    Infantryman's Axiom; Always cheat, always win.
  • cgracey wrote: »
    At first, I was kind of alarmed that there were so many wire-size issues.

    The guy that did this work is about 25 years old and he lives near Mexico City. The layout tools tell him when he's made a design-rule violation or didn't match my schematic. He relies on those tools to do his job, of course. The crazy thing is that he doesn't know electronics! He doesn't really need to, although that knowledge would have saved the need to make so many edits, in this case. Had I thought to put explicit wire-width instructions into my schematic for him, he would have followed them. I just assumed that if he saw a wide, multi-gate, min-length transistor, he would know to increase the metal connection widths, but that wasn't the case.

    In the end, he did a pretty good job and there were just a handful of things that needed revisiting. I've spent days tracing out high-current signal and power routes, making sure they are sufficient, or finding ways to make them sufficient. I think we've got them all fixed now and this layout is production-worthy.

    EDA tools are leaned on heavily by chip designers, these days, to let them know if they have done things right. If the tool tells them they're done, they're done! The tool just checks for design-rule compliance and schematic match, without regard to things like an air compressor being plugged in via two series'd lamp extension cords. This is a funny by-product of skill specialization. It never occurred to me that the person doing our layout work wouldn't know electronics. He did a lot of work pretty quickly, though, and it was generally high-quality. We just had a few things to patch up, in the end.

    Seriously? I'd think theywpuld hire electronics engineers. What sort of background ARE they hiring?
    Particularly patient proactive practice positively predicates practically precise poly-processor Parallax Propeller programming paradigms.

    .
  • Seriously? I'd think they would hire electronics engineers. What sort of background ARE they hiring?

    My thoughts exactly Michael!!!
    cgracey wrote: »
    EDA tools are leaned on heavily by chip designers, these days, to let them know if they have done things right.

    Not if the layout designer is worth their weight. Yes, the EDA tools should be used to confirm that there are no violations, but to rely on the tool without any fundamental knowledge is like asking a 3 year old to drive your car 10 miles to the grocery store simply because he has road experience he learned on his BIG Wheel.



    Beau Schwabe -- Submicron Forensic Engineer
    www.Kit-Start.com - bschwabe@Kit-Start.com ෴෴ www.BScircuitDesigns.com - icbeau@bscircuitdesigns.com ෴෴

  • cgraceycgracey Posts: 10,151
    edited May 25 Vote Up0Vote Down
    Humans can't worry about millions of nets in modern chips. The placement and routing must be automated and managed through things akin to policies via configuration scripts. They have to tweak the scripts until the last thousand violations all disappear at once. A lifetime would be insufficient to manually place and route even the P2. The people that drive the scripts know what is correct and incorrect, or optimal and wasteful, and they manage the tool to get the best outcome they can.
  • cgracey wrote: »
    Humans can't worry about millions of nets in modern chips. The placement and routing must be automated and managed through things akin to policies via configuration scripts... ...I've spent days tracing out high-current signal and power routes, making sure they are sufficient, or finding ways to make them sufficient. I think we've got them all fixed now and this layout is production-worthy.
    .... I See, lets hope you found them all. Poor IR management is a killer in IC layout and tools don't always catch these kind of problems. Power management skills are essential before any cells are placed, and never should be done as an after thought. In this line of work, you can't make any assumptions, especially dealing with the abilities of multiple people and even the ability of the tool. You must be 100% certain. .... Another car analogy here --> You can never assume that the other guy sees you, you must be alert and ready for anything that comes your way. Assumptions will get you in trouble real quick.



    Beau Schwabe -- Submicron Forensic Engineer
    www.Kit-Start.com - bschwabe@Kit-Start.com ෴෴ www.BScircuitDesigns.com - icbeau@bscircuitdesigns.com ෴෴

  • cgracey wrote: »
    Humans can't worry about millions of nets in modern chips. The placement and routing must be automated and managed through things akin to policies via configuration scripts... ...I've spent days tracing out high-current signal and power routes, making sure they are sufficient, or finding ways to make them sufficient. I think we've got them all fixed now and this layout is production-worthy.
    .... I See, lets hope you found them all. Poor IR management is a killer in IC layout and tools don't always catch these kind of problems. Power management skills are essential before any cells are placed, and never should be done as an after thought. In this line of work, you can't make any assumptions, especially dealing with the abilities of multiple people and even the ability of the tool. You must be 100% certain. .... Another car analogy here --> You can never assume that the other guy sees you, you must be alert and ready for anything that comes your way. Assumptions will get you in trouble real quick.

    For full-custom circuits, such minding is needed.

    For auto-generated digital circuits, tools are relied on for all but top-level floorplanning, which includes power grid perimeter, space, and trace. IR-drop and signal-integrity are managed through scripts, along with clock tree, scan chain, BIST, and whatever else is needed.
  • MIchael_MichalskiMIchael_Michalski Posts: 106
    edited May 25 Vote Up0Vote Down
    Seriously? I'd think they would hire electronics engineers. What sort of background ARE they hiring?

    My thoughts exactly Michael!!!
    cgracey wrote: »
    EDA tools are leaned on heavily by chip designers, these days, to let them know if they have done things right.

    Not if the layout designer is worth their weight. Yes, the EDA tools should be used to confirm that there are no violations, but to rely on the tool without any fundamental knowledge is like asking a 3 year old to drive your car 10 miles to the grocery store simply because he has road experience he learned on his BIG Wheel.

    The future of course is more and more sophisticated automated layout tools, using more and more sophisticate algorithms. All the machine learning and AI technology will most certainly be applied. And that's where we REALLY end up with problems, where the layout tools no longer deterministicy apply design rules but instead make new ones and even alter the design in that fuzzy heuristic sort of way that neural networks (such as Chip) do.

    Particularly patient proactive practice positively predicates practically precise poly-processor Parallax Propeller programming paradigms.

    .
  • From the way I see it, the custom parts of the P2 (the ring frame with custom I/O including the analog part and pull-ups and pull-downs) have been a nightmare (and very expensive) to integrate with the tools that implement the majority of the design.
    The P2 is way too complex to be done manually as the P1 was. Even the P1 wouldn't be manually done today.
    Did you see where a significant proportion (forget the %) of the transistors are used for testing each dice works properly. AFAIK OnSemi requires this.
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • The P1 and P2 are really not as complex as we are led to believe. Much of the complexity comes from a constant moving design target as well as a moving process target perpetually driven by the lowest bidder.


    Beau Schwabe -- Submicron Forensic Engineer
    www.Kit-Start.com - bschwabe@Kit-Start.com ෴෴ www.BScircuitDesigns.com - icbeau@bscircuitdesigns.com ෴෴

  • JRetSapDoogJRetSapDoog Posts: 771
    edited May 26 Vote Up0Vote Down
    Guess complexity is relative; however, I'm guessing that not so many individuals have taken it upon themselves to bring a microcontroller to market from scratch. Anyway, in designing something, deciding *what* to do is probably as hard as pulling it off. Change is almost unavoidable for anything non-trivial, I would think. And when one is mostly working alone and putting up one's own resourses to do development--rather than being paid by an employer at little personal risk--it's hard, in a word. And only those that have done it could really understand. Among other things, one must draw on inner resources to stay motivated and on track, since no boss is looking over one's shoulders. And one hopes to create something that is useful and hopefully marketable in a world with lots of existing solutions that were mostly brought about by big teams. That all seems pretty daunting to me, regardless of the transistor count and process details. Moreover, do we only want chips that takes hundreds of millions of dollars to get to market? Guess they're okay for cell phones. Anyway, the P2 road has definitely been a long one, and I'm sure that with hindsight it could be a shorter road. But that's just how it is.
  • You know Beau, I really appreciate what you did at your time at Parallax. I used some of your code to learn how to bit bang fast transmissions.

    Without you there might not be a P1 or P2 at all.

    I also understand that loosing your job at Parallax was not expected by you at that time, but you by yourself stated for a couple of times now here in this forums, that you would not have that farm you have now and that new and obviously exiting different career as forensic engineer.

    But you still seem to have a grudge with Chip, and in my not so humble opinion this does not belong here.

    Compared to say a current intel processor the P2 is tiny. You are for sure right in your technical opinion about the importance of Power management and the importance of teamwork of them people involved, I have no clue at all how this magic works.

    But what I am very sure of is that no person in this world ever understood WHY the automated tools produced the latest intel or amd chips like they are, and I am also pretty sure that nobody routed anything there by hand.

    So you bashing Chip for using this process for a relative small chip is quite astonishing to me.

    And honest question, asking for honest answer,

    Do you really believe Chip and OnSemi are running full speed the wrong path? And if so, how do other companies manage that?

    I do not have any stakes in this, I am just curious.

    Mike
    I am just another Code Monkey.
    A determined coder can write COBOL programs in any language. -- Author unknown.
    Press any key to continue, any other key to quit

    The key words "MUST", "MUST NOT", "REQUIRED", "SHALL", "SHALL NOT", "SHOULD", "SHOULD NOT", "RECOMMENDED", "MAY", and "OPTIONAL" in this post are to be interpreted as described in RFC 2119.
  • To All,

    Addressing some of msrobots statements:

    "I also understand that loosing your job at Parallax was not expected by you at that time, but you by yourself stated for a couple of times now here in this forums, that you would not have that farm you have now and that new and obviously exiting different career as forensic engineer." ... All true, but at a personal cost I would not wish upon anyone.


    "But you still seem to have a grudge with Chip, and in my not so humble opinion this does not belong here." ... It's not a grudge, but more so there is a right way to design an IC and a wrong way or a seemingly lack of solid direction approach. There are many things I see in the forums that are red flags. Chip mentions things that need to be done or should be done that were already implemented such as ESD protection. Comments like this are a concern because it makes me wonder if the structures were completely understood by him or just removed. TSMC standard ESD structures for the 180nm process was implemented as well as spark gap structures that might have just looked like pieces of metal to a casual observer when indeed they were functional and engineered to break down at a specific voltage .... i.e. 3V per nm when objects are round or parallel (much less V/nm when you introduce points). This was applied to every I/O.


    "Do you really believe Chip and OnSemi are running full speed the wrong path? And if so, how do other companies manage that?" ...
    He needs to prove his current analog IP in the current process he is using and most important stick to that process and not change it until the project is complete. Never change the target process mid-stream. As far as I can tell he is all over the place with this, between design houses, and processes under the hood of 180nm. The digital logic needs to be locked down, and tested again with the analog to make sure there isn't substrate noise from the digital logic coupling into the analog design, and if so that needs to be addressed. It is an iterative process that should not be taken lightly. The tools can only take you so far, but the real interface when analog is involved, needs empirical testing. Empirical testing is how it is managed, because the spice model will never match the real world. there are just too many variables... the length of a wire as well as the thickness of a wire has an effect. All of us know this, it's no different than a normal wire that has a certain resistance per foot based on the gauge of the wire, except in layout you measure the resistance in Ohms per square and you count the number of squares based on the width of the wire and the wire length. A single contact used to change metal layers is typically 10 Ohms per contact. For signals this usually isn't a huge deal, but where it can be a BIG problem is for power considerations. The "IR drop" (<- Current drop due to resistance) in a situation like this can be dramatic. Chip posted awhile back where power was only coming in from one corner of the block and only had a few power straps. I called him out on it, only because it was a concern. If the IR drop is too large, substrate noise is too large, and there isn't adequate substrate taps, then you run the risk of latch-up where the lateral parasitic NPN and PNP transistors form an SCR that latches ON usually causing catastrophic failure.


    So take what I say with a grain of salt... if you listen great, if not, then you can't say something wasn't mentioned when there is a problem that can't be explained. ... OR I can just not say anything and sit back and watch everything unfold. I've been in this forum for 26 years, I have seen and heard it all and the general rule is, if you can't take it, then don't put it out there.

    Good luck


    Beau Schwabe -- Submicron Forensic Engineer
    www.Kit-Start.com - bschwabe@Kit-Start.com ෴෴ www.BScircuitDesigns.com - icbeau@bscircuitdesigns.com ෴෴

  • Beau,
    I have remained silent regarding your comments that, IMHO, have not been quite proper. It's a shame.

    You provided a lot of good input to the P2 - I don't know about the P1. I also learnt quite a lot from your info in the earlier P2 days.

    But things have changed, and it seems you may not have moved with the times. Gone are the days of manual layout, except for small designs on old processes. The tools now do it. It's just a fact of life, just as most code is no longer in assembler. Same goes with pcb design. I still route my pcbs by hand, but I don't do anything complex any more either.

    Chip does have an analog chip(s) in hand and he has tested them. They arrived a few months ago.

    Sure, some of the decisions in using some of the design houses and designers have resulted in expensive learning curves. Unfortunately this is business reality. Lots of professionals not up to scratch, but happily take the money. It has also taken time to get to the good people within OnSemi. And I am certain they are not OnSemi's best - they will be reserved for the really good customers. Reality rules!

    But the current P2 process with OnSemi seems to be progressing well. OnSemi requires the tools to pass the design before they will proceed to silicon, and that means the tools also route their own test logic inside the die. By following this requirement, OnSemi virtually guarantees successful silicon. I don't even know if they will accept hand routed designs any more because they cannot test them. This has been a major problem with the ring frame which includes the I/O, as you are well aware.

    Please, let's move on positively.
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
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