Custom Layout Mods

2»

Comments

  • jmg wrote: »
    cgracey wrote: »
    ...

    Meanwhile, I rented an ESD zapper gun, since my old one went kaput, and I've been zapping the prior test chip. It has the same ESD circuits as the new one, so it can reveal any ESD weakness in our design. Surprisingly, the chip failed ESD testing miserably! The problem is that the core ground (GND) and I/O ground (GIO), while normally at the same potential, can get a huge differential during a zap.

    The core ground and I/O grounds are not shorted together on the die, but are both bonded down to the exposed pad, which becomes BOTH grounds. This was done to keep core ground currents, which are quite high on the die and cause ~25mV differences on what should be the same "ground", isolated from the I/O grounds which may be doing ADC and DAC operations that would be really compromised by ground noise. Anyway, during an ESD zap, those core and I/O grounds could be 50V apart for a few nanoseconds. This was causing my level shifters to blow out, as delicate NMOS gates were exposed to this havoc.

    In order to fix this, I need to add a resistor and a small ESD clamp on each of the cross-domain connections where the NMOS transistors are being driven.

    I had plenty of ESD protection where I thought it was needed, but totally missed the other vulnerabilities. Today I'm working on the schematic for the PAD ring elements to fix all this.

    That sounds like it will slow signals down ? (and may not give best protection)

    Can you not add some 'fat' back to back diodes (one may be there already) between the two grounds ?
    In normal operation, they are mV separate, but in ESD event, the diodes ensure the GNDs cannot wander too far apart ?


    Yes, I'd like to get away with just big back-to-back diodes. I'm looking through the PDK now to see how to call this out.

    If we could keep the grounds close together, there shouldn't be a need for the resistor-clamp ESD circuits between ground domains. Those circuits do add about 500ps of delay.
  • Assuming this shuttle run goes better than the P2 Hot one did, even if it's not perfect what are the chances some of us might snag one of the beta chips for a little testing of our own? I would be willing to lay out a bit of coin just for the coolness factor of having one of the functional prototypes.
  • This shuttle doesn't have any cogs as such. It basically the ring frame without smarts, word to io pins for testing.
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
Sign In or Register to comment.