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  • jmg wrote: »
    cgracey wrote: »
    ...

    Meanwhile, I rented an ESD zapper gun, since my old one went kaput, and I've been zapping the prior test chip. It has the same ESD circuits as the new one, so it can reveal any ESD weakness in our design. Surprisingly, the chip failed ESD testing miserably! The problem is that the core ground (GND) and I/O ground (GIO), while normally at the same potential, can get a huge differential during a zap.

    The core ground and I/O grounds are not shorted together on the die, but are both bonded down to the exposed pad, which becomes BOTH grounds. This was done to keep core ground currents, which are quite high on the die and cause ~25mV differences on what should be the same "ground", isolated from the I/O grounds which may be doing ADC and DAC operations that would be really compromised by ground noise. Anyway, during an ESD zap, those core and I/O grounds could be 50V apart for a few nanoseconds. This was causing my level shifters to blow out, as delicate NMOS gates were exposed to this havoc.

    In order to fix this, I need to add a resistor and a small ESD clamp on each of the cross-domain connections where the NMOS transistors are being driven.

    I had plenty of ESD protection where I thought it was needed, but totally missed the other vulnerabilities. Today I'm working on the schematic for the PAD ring elements to fix all this.

    That sounds like it will slow signals down ? (and may not give best protection)

    Can you not add some 'fat' back to back diodes (one may be there already) between the two grounds ?
    In normal operation, they are mV separate, but in ESD event, the diodes ensure the GNDs cannot wander too far apart ?


    Yes, I'd like to get away with just big back-to-back diodes. I'm looking through the PDK now to see how to call this out.

    If we could keep the grounds close together, there shouldn't be a need for the resistor-clamp ESD circuits between ground domains. Those circuits do add about 500ps of delay.
  • Assuming this shuttle run goes better than the P2 Hot one did, even if it's not perfect what are the chances some of us might snag one of the beta chips for a little testing of our own? I would be willing to lay out a bit of coin just for the coolness factor of having one of the functional prototypes.
  • This shuttle doesn't have any cogs as such. It basically the ring frame without smarts, word to io pins for testing.
  • cgraceycgracey Posts: 9,011
    edited February 8 Vote Up0Vote Down
    I've been in Colorado Springs all week at Treehouse Design. We are wrapping up the layout changes for the Prop2 pad ring. Things are really coming together.

    Here is a picture of the lady who's been doing most of the work. Her name is Judy and she is really on top of things.

    Judy's husband Mike works here, too. He's laying out the new ESD clamping diodes and now-simplified output transistors. Today we had a few calls with a really good engineer at OnSemi who helped us straighten out some errors we were having. Tomorrow morning, the ESD clamps should come together nicely.

    Meanwhile, Judy is here at 9pm going through the pads and bringing the signals out to the core, and generally tidying everything up. We also increased the top metal layer to 3.0 micrometer thickness from 0.8. This entails some other edits. Everything is shaping up really well.
    2048 x 1152 - 1M
  • idbruceidbruce Posts: 5,642
    edited February 8 Vote Up0Vote Down
    Chip

    It almost sounds like the new CNC just might be running on a P2. However I will still need a development board.

    I wonder who will finish first... I will be welding up the frame very shortly... and my stepper power supplies should arrive Friday.

    Either way, it appears we are both making nice progress.


    Novel Solutions - http://www.novelsolutionsonline.com/ - Machinery Design • - • Product Development
    "Necessity is the mother of invention." - Author unknown.

  • cgraceycgracey Posts: 9,011
    edited February 8 Vote Up0Vote Down
    idbruce wrote: »
    Chip

    It almost sounds like the new CNC just might be running on a P2. However I will still need a development board.

    I wonder who will finish first... I will be welding up the frame very shortly... and my stepper power supplies should arrive Friday.

    Either way, it appears we are both making nice progress.

    That's excellent!

    Maybe you will be done first, though.

    Things on Prop 2 really are moving forward.
  • I'm "just" a forum member, but hats off to Judy and Mike for putting in the long hours to help with Chip's chip. Hope that Judy can sleep late tomorrow and come in around lunch time. It's great that you folks were able to arrange a phone meeting with OnSemi (the right help at the right time, it sounds like). Now, that nearly quadruple increase in the thickness of the top metal layer sounds interesting. Wonder what the story is behind that (and whether Chip will still be able to "peer" through it with his special second-hand machine). Anyway, sounds like great progress is being made. Thanks for the "Colorado update" with the picture of Judy happily slaving away, Chip.
  • Chip

    As much as I enjoy your endeavors, I am sure you would enjoy mine, but I do not provide information to the public about my projects like you do. My current project is a serious one and I will be filing a patent. I know that you are not a big fan of patents, but I am. Either way, I would love to hear your input on my current endeavor and how the P2 could benefit this machine. I am hoping to meet you someday, where Electronical meets Mechanical.


    Novel Solutions - http://www.novelsolutionsonline.com/ - Machinery Design • - • Product Development
    "Necessity is the mother of invention." - Author unknown.

  • Way to go Chip (and Treehouse friends)! :cool:
    Melbourne, Australia
  • cgracey wrote: »
    I've been in Colorado Springs all week at Treehouse Design. We are wrapping up the layout changes for the Prop2 pad ring. Things are really coming together.

    It's interesting, and satisfying, to see a project you've been working on for a long time suddenly start coming together like that. Enjoy.

    Sandy

    Infantryman's Axiom; Always cheat, always win.
  • cgracey wrote: »
    At first, I was kind of alarmed that there were so many wire-size issues.

    The guy that did this work is about 25 years old and he lives near Mexico City. The layout tools tell him when he's made a design-rule violation or didn't match my schematic. He relies on those tools to do his job, of course. The crazy thing is that he doesn't know electronics! He doesn't really need to, although that knowledge would have saved the need to make so many edits, in this case. Had I thought to put explicit wire-width instructions into my schematic for him, he would have followed them. I just assumed that if he saw a wide, multi-gate, min-length transistor, he would know to increase the metal connection widths, but that wasn't the case.

    In the end, he did a pretty good job and there were just a handful of things that needed revisiting. I've spent days tracing out high-current signal and power routes, making sure they are sufficient, or finding ways to make them sufficient. I think we've got them all fixed now and this layout is production-worthy.

    EDA tools are leaned on heavily by chip designers, these days, to let them know if they have done things right. If the tool tells them they're done, they're done! The tool just checks for design-rule compliance and schematic match, without regard to things like an air compressor being plugged in via two series'd lamp extension cords. This is a funny by-product of skill specialization. It never occurred to me that the person doing our layout work wouldn't know electronics. He did a lot of work pretty quickly, though, and it was generally high-quality. We just had a few things to patch up, in the end.

    Seriously? I'd think theywpuld hire electronics engineers. What sort of background ARE they hiring?
    Particularly patient proactive practice positively predicates practically precise poly-processor Parallax Propeller programming paradigms.

    .
  • Seriously? I'd think they would hire electronics engineers. What sort of background ARE they hiring?

    My thoughts exactly Michael!!!
    cgracey wrote: »
    EDA tools are leaned on heavily by chip designers, these days, to let them know if they have done things right.

    Not if the layout designer is worth their weight. Yes, the EDA tools should be used to confirm that there are no violations, but to rely on the tool without any fundamental knowledge is like asking a 3 year old to drive your car 10 miles to the grocery store simply because he has road experience he learned on his BIG Wheel.




    Beau Schwabe -- Submicron Forensic Engineer
    www.Kit-Start.com - bschwabe@Kit-Start.com ෴෴ www.BScircuitDesigns.com - icbeau@bscircuitdesigns.com ෴෴

    Seriously at this point in the game "the ship has sailed" and "I have no expectations" <- said two brothers we ALL know
  • cgraceycgracey Posts: 9,011
    edited 6:33AM Vote Up0Vote Down
    Humans can't worry about millions of nets in modern chips. The placement and routing must be automated and managed through things akin to policies via configuration scripts. They have to tweak the scripts until the last thousand violations all disappear at once. A lifetime would be insufficient to manually place and route even the P2. The people that drive the scripts know what is correct and incorrect, or optimal and wasteful, and they manage the tool to get the best outcome they can.
  • cgracey wrote: »
    Humans can't worry about millions of nets in modern chips. The placement and routing must be automated and managed through things akin to policies via configuration scripts... ...I've spent days tracing out high-current signal and power routes, making sure they are sufficient, or finding ways to make them sufficient. I think we've got them all fixed now and this layout is production-worthy.
    .... I See, lets hope you found them all. Poor IR management is a killer in IC layout and tools don't always catch these kind of problems. Power management skills are essential before any cells are placed, and never should be done as an after thought. In this line of work, you can't make any assumptions, especially dealing with the abilities of multiple people and even the ability of the tool. You must be 100% certain. .... Another car analogy here --> You can never assume that the other guy sees you, you must be alert and ready for anything that comes your way. Assumptions will get you in trouble real quick.




    Beau Schwabe -- Submicron Forensic Engineer
    www.Kit-Start.com - bschwabe@Kit-Start.com ෴෴ www.BScircuitDesigns.com - icbeau@bscircuitdesigns.com ෴෴

    Seriously at this point in the game "the ship has sailed" and "I have no expectations" <- said two brothers we ALL know
  • cgracey wrote: »
    Humans can't worry about millions of nets in modern chips. The placement and routing must be automated and managed through things akin to policies via configuration scripts... ...I've spent days tracing out high-current signal and power routes, making sure they are sufficient, or finding ways to make them sufficient. I think we've got them all fixed now and this layout is production-worthy.
    .... I See, lets hope you found them all. Poor IR management is a killer in IC layout and tools don't always catch these kind of problems. Power management skills are essential before any cells are placed, and never should be done as an after thought. In this line of work, you can't make any assumptions, especially dealing with the abilities of multiple people and even the ability of the tool. You must be 100% certain. .... Another car analogy here --> You can never assume that the other guy sees you, you must be alert and ready for anything that comes your way. Assumptions will get you in trouble real quick.

    For full-custom circuits, such minding is needed.

    For auto-generated digital circuits, tools are relied on for all but top-level floorplanning, which includes power grid perimeter, space, and trace. IR-drop and signal-integrity are managed through scripts, along with clock tree, scan chain, BIST, and whatever else is needed.
  • MIchael_MichalskiMIchael_Michalski Posts: 71
    edited 8:12PM Vote Up0Vote Down
    Seriously? I'd think they would hire electronics engineers. What sort of background ARE they hiring?

    My thoughts exactly Michael!!!
    cgracey wrote: »
    EDA tools are leaned on heavily by chip designers, these days, to let them know if they have done things right.

    Not if the layout designer is worth their weight. Yes, the EDA tools should be used to confirm that there are no violations, but to rely on the tool without any fundamental knowledge is like asking a 3 year old to drive your car 10 miles to the grocery store simply because he has road experience he learned on his BIG Wheel.

    The future of course is more and more sophisticated automated layout tools, using more and more sophisticate algorithms. All the machine learning and AI technology will most certainly be applied. And that's where we REALLY end up with problems, where the layout tools no longer deterministicy apply design rules but instead make new ones and even alter the design in that fuzzy heuristic sort of way that neural networks (such as Chip) do.

    Particularly patient proactive practice positively predicates practically precise poly-processor Parallax Propeller programming paradigms.

    .
  • From the way I see it, the custom parts of the P2 (the ring frame with custom I/O including the analog part and pull-ups and pull-downs) have been a nightmare (and very expensive) to integrate with the tools that implement the majority of the design.
    The P2 is way too complex to be done manually as the P1 was. Even the P1 wouldn't be manually done today.
    Did you see where a significant proportion (forget the %) of the transistors are used for testing each dice works properly. AFAIK OnSemi requires this.
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