Original Title Edited. Was : 'General Planning - First IC samples 2017 (Q4)'
The purpose of this thread was to check the grade of completeness of P2 development, and the grade of commitment for completion. It was an attempt to obtain any more detailed information than just "the P2 will be done when it is ready."
P2 is still in alpha stage, even if the instruction set is frozen. Frozen doesn't mean completed, and doesn't mean it cannot change.
Ken said that there is no schedule planned, and that any schedule or plan depends on Chip. And Chip just says what is the next step he would do and that is. You all can check bellow the responses from Ken and Chip.
(Space reserved for official Planning.)
This is the planning if there is no official plan:
1) Test instruction set (1 month, end of 1st Quarter).
Start compiler and documentation.
2) Final release v17 (Fix bugs).
Send verilog to treehouse (begining of April)
3) Shuttle (2Q)
4) Get first shuttle ICs and send to package vendor (3Q).
5) Deliver first ICs before end of year (end of 3Q/begining of 4Q).