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New DE10_lite Max10 FPGA board perfect forr P1v experiments

ozpropdevozpropdev Posts: 2,102
edited November 2016 in Propeller 1 Vote Up0Vote Down
Here's a nice little FPGA board for those playing with P1V's.

Features:
Max10 10M50 FPGA
10 leds
10 switches
2 buttons
6 x 7 segment displays
4 bit VGA
64MB SDRAM
Accelerometer
Arduino header
40 pin header

http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=english&No=1021

Here's the resource usage for a 64IO,32Kb Hub,8 cog P1V
Family	MAX 10
Device	10M50DAF484C7G
Total logic elements	17,207 / 49,760 ( 35 % )
Total registers	5973
Total pins	74 / 360 ( 21 % )
Total memory bits	655,360 / 1,677,312 ( 39 % )
Total PLLs	1 / 4 ( 25 % )

Board should fit 2 x 8 cog P1V's easily.
Melbourne, Australia
1177 x 1049 - 390K
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Comments

  • 53 Comments sorted by Date Added Votes
  • David BetzDavid Betz Posts: 11,943
    edited November 2016 Vote Up0Vote Down
    I was excited about working on extensions to P1V until I tried just compiling it in my old 2010-vintage Windows laptop. It took so long that I realized it wasn't really going to be possible for me to tweak the code. I pretty much depend on fast turnaround when making software changes and having to wait an hour for a compile reminds me of being back in the punched card days were I sumitted a deck of cards and came back hours later or the next day to find out whether my program worked. What is the compile time like on a modern computer?
  • On my PC (1 year old) a Max10 compile that uses 80% resources takes ~10 mins.
    I have found that Max10 compiles ~ 3x faster than a Cyclone V compiles.
    The closer you get to maxing out (pardon the pun) your resources the more the compile time blows out.
    I purchased this PC just to get Quartus moving along quicker.
    I still have had cyclone V compiles > 1 hout. :(
    Melbourne, Australia
  • BTW A DE10_lite should be able to squeeze in 2 x P2 cogs! :)
    Melbourne, Australia
  • This looks really interesting compared to the BeMicroMAX10 I have been using which can get 3-4 cogs at best.

    It also still has plain SDRAM which I had found on DE-0 nano and the BeMicroMAX10 boards could be customized easier to interface with the P1V than trying to use the DDR type memories using inbuilt controller block IP.

    Thanks for sharing ozpropdev!
  • By the way ozpropdev, if you have one of these boards can you tell me what speed SDRAM parts were they using on it (i.e. does it have the -7 or -6 suffix)? The -6 variant potentially allows up to 166MHz clocking, so also supporting 2x80MHz operation with CL=3 which is nice on a P1V if you want to run the core at 80MHz.

    A close up photo I saw in the user manual showed the slower/cheaper -7ns part fitted so its a fair bet that it is going to be that part used in production too. In theory that part is rated only up to 143MHz though you also may be able to push to 160 if you get lucky. The current DE0 nano and BeMicroMAX10 boards I have both use a 7ns part.
  • Roger
    It's the -7 version. :(
    1056 x 592 - 324K
    Melbourne, Australia
  • Hmmm would be fairly easy to desolder and change over.

    I'm placing a mouser order tomorrow and they have the -6 grade in stock, should we give it a try?
  • Thanks Brian. Also thanks for the offer Tubular but I'd better not for now. I'm in the midst of starting something else with Max10 and probably don't need the added distraction. :-) But I do like the look of this new FPGA board compared to De0-nano for P1V experimenting and might score one sometime then investigate the memory stuff again.
    Cheers.
  • Regarding the compile times, are they like cyclone iv or v ?
  • Ale wrote: »
    Regarding the compile times, are they like cyclone iv or v ?
    I have found that Max10 compile times are more like Cyclone IV times.
    Cyclone V is notably slower on all of my builds.
    P1V 32K Hub,32 I/O Compile times Quartus Prime Ver. 16.1
    
    Cyclone IV	3:02
    Cyclone V	5:49
    Max10		3:02  (same as Cyclone IV in this case)
    


    Melbourne, Australia
  • So, they are cyclone ivs in disguise :), nice board...
  • My son is taking a digital systems class at UC Davis, and they have assigned the DE10-Lite for the lab work. Wow--very different level from when I was in school. Setting it up on his Mac seems too problematic, so he is thinking to buy relatively cheap PC or Linux box. Any recommendations? I see discussion of compile speed on this thread. What should he watch out for? I'm not sure what kind of projects they will have for the class, but I'd like to think in advance of what it would take to do the P1V stuff too.

  • Setting it up on his Mac seems too problematic, so he is thinking to buy relatively cheap PC or Linux box. Any recommendations?

    Why not just use Boot Camp on his Mac to install Windows or Linux?

    Surely that is the cheapest option, even if it means reboots to switch.

    Another alternative would be to use a VM to run the software, which gives better integration between work environments, no reboots to switch, but might suffer some performance loss.
  • Terasic Web page says $50, but it's closer to $100 on Digikey...
    DE0 nano is hair cheaper, but I guess this has more features?

    BTW: The cheapest board on Digikey looks to be the "MachXO3L Starter Kit" from Lattice.
    It's only $25...
    Any chance the P1V would work on that?
    Prop Info and Apps: http://www.rayslogic.com/
  • Tracy AllenTracy Allen Posts: 6,215
    edited January 23 Vote Up0Vote Down
    The Mac is a laptop, I think maxed out with music and music software like ProTools. He's thinking maybe the DE-10 tools could run from reboot to an external hard drive.
    https://9to5mac.com/2017/08/31/how-windows-10-mac-boot-camp-external-drive-video/
  • I usually dig up someone's discarded old desktop PC and put a new motherboard/DRAM/CPU in it. That way you get all the accessories for free. If the case is new enough then even the power supply can be reused.

    HDD may need replaced, depends on its age/size. If it's already a 200 GB or bigger then try using it. A SSD does wonders for load times but that is a relative premium.

    The big downer at the moment is DRAM prices are peaking. Which is a frustration because DRAM is the one thing you can easily have excess of and is well worth it ... normally.

    In fact, it seems all chip prices are all on their way up. Even nVidia have said people should only buy the GPUs they need because they can't keep up with demand.
    “What car did you learn to drive stick shift on?” == “What was the make and model of your first car?” -> Password reset! -- https://krebsonsecurity.com/2018/04/dont-give-away-historic-details-about-yourself/
  • Rayman wrote: »
    Terasic Web page says $50, but it's closer to $100 on Digikey...
    DE0 nano is hair cheaper, but I guess this has more features?

    I see it for $55 on Terasic, but that's for Academia.
    Otherwise they sell for $85 or more where I've seen them.

    Any com port in a storm.
    Floating point numbers will be our downfall; count on it.
    Imagine a world without hypothetical situations.
  • RaymanRayman Posts: 8,465
    edited January 24 Vote Up0Vote Down
    I see this FPGA has more capacity than the DE0 nano.
    The low cost MachXO3L thing doesn't appear to have anywhere near the needed capacity...

    Does the original post show capacity with the P1 ROM Character Map included?
    It looks like they had to leave this off in order to fit in the DE0 nano...
    Prop Info and Apps: http://www.rayslogic.com/
  • Rayman wrote: »
    Does the original post show capacity with the P1 ROM Character Map included?
    It looks like they had to leave this off in order to fit in the DE0 nano...
    Ray
    The original build shown above does include 32k hub, character rom and math tables too. (39% memory bits used)
    Melbourne, Australia
  • He's decided to wait until after the second lab session to get the software set up on his own computer. The software is memory intensive, says it wants 40 GB, many components, procedures and options. Even in the lab where it was already installed it was tough going; everyone in the class had trouble getting anything at all to compile, and the single lab instructor was totally overloaded trying to resolve student difficulties one at a time.

    I guess that you folks who use this on a regular basis at some point have all or most of the kinks worked out, right?

    It makes me appreciate (again) the simplicity and directness of the Parallax software. Back when I was learning digital logic, we had TTL or CMOS gates and latches, to connect with wires. Now they have to learn even the basics using tools for building skyscrapers, not cottages.
  • Wow. What FPGA tools are they using? I have Quartus running on an Surface Pro with 8GB RAM, 256GB SSD. It builds the P1V and my experiments with Verilog easily. Previously I used Quartus on even lesser capacity Linux PC's.

    I suspect this lab would have an easier time using small Lattice FPGAs and the Free and Open Source IceStorm tools. Easy to install, quick and easy to use. Surely their projects will not be so big as to need more than that.


  • Quartus installed fine for me but there was a problem getting P1V to compile. IIRC it required a patch from Altera.

    However, Lattice software was a PITA to install. Required lots of searching and also Comms with Lattice to eventually get it running, and I don't mean compiling!!! Their protection mechanism is totally awful.

    Part of the uni course is to use software, and to that end that means proper software used by business. Here, I would have to say, Lattice software is not ready for prime time. IMHO only Quartus and Xilinx (forget what it's called these days) comply. The Open Source software is no in any way ready for prime time, so it's a waste teaching it. And while Lattice FPGAs are prime time, their software is just unusable, installation wise!
  • Cluso99,
    Part of the uni course is to use software, and to that end that means proper software used by business.
    No doubt. But when getting that software working is eating multiple tab sessions it is wasting a lot of valuable student time, not to mention that of the TA's and Profs. At that point something has gone badly wrong. Perhaps other approaches are called for...
    The Open Source software is no in any way ready for prime time, so it's a waste teaching it.
    Depends what you mean by "prime time". Also I'd say that an undergraduate uni course is not prime time.

    Certainly the tools available for creating FPGA designs are currently very limited. Basically only IceStorm/Yosys which are only usable for a few specific Lattice devices. Hardly surprising since the inner workings of FPGA's are all a closely guarded secret and a few guys had to reverse engineer the whole thing. An amazing feat by the way.

    If the purpose of the course is to teach electronics, logic design, Verilog, getting FPGA's working etc then I would suggest the Open Source tools are perfectly adequate. The simulators GHDL, Verilator, Icarus work very well. IceStorm/Yosys is very easy to get working and create beginner level designs in actual FPGA's.

    It's certainly worth teaching such things at uni. Surely the purpose of higher education is to aim somewhat higher than just following the current state of play in the industry?


  • Imho they need to choose either an Altera or Xilinx FPGA board. The software provided by both companies is prime time and works.

    Lattice FPGAs might be good, but the software is severely hampered by over enthusiastic copy protection, and on free software to boot! Something's not right here!
  • Yes. I have not tried to download and install any Lattice tools yet but from what I read they seem to be out of touch with the times with all that copy protection stuff. Why do that?


  • Lattice Diamond is by far the easiest FPGA IDE to use.
    I had no problems to install Diamond and IceCube2 on my Windows 7 PC. All you need is the MAC number of your Ethernet port for the copy protection.

    But I have not installed the Active-HDL simulator, maybe it has its own copy protection. I just don't need it.
    It may be more problematic to install it on Linux or MAC.


    The free icestorm tools are command line tools and not well comparable with an IDE. I use it on a RasPI with Geany. Geany's editor has Verilog highlighting and starts a makefile for the project, so it's all automated. To synthesize and download a modified Verilog project, I need to press a single function key. Easier than every other tool. The whole synth-, place and route takes about 1/3 of the time of IceCube (and that is on a PI, while Icecube runs on a 2 GHz PC).

    Andy
  • Diamond and IceCube2 work nicely on W10 once you get the copy protection working. But if you don't get it right the first time it's a real PITA to fix it. The instructions are not clear, so you are likely to fail the first time.
    But why the copy protection that is tied to the MAC address on your pc/laptop when it's free software??? It just doesn't make any sense!!!
  • Cluso99 wrote: »
    ...
    But why the copy protection that is tied to the MAC address on your pc/laptop when it's free software??? It just doesn't make any sense!!!

    Lattice wants to keep control. The license is valid for one year only. You have to renew it every year. So they can always decide that it is no longer free.
    For sure they will not do it as long as the competitors have free tools.
  • Ariba,
    For sure they will not do it as long as the competitors have free tools.
    I don't understand that part.

    The competitors do have free tools but Lattice still does that.

  • Hey Ariba!

    Using the Lattice tools have you been able to get a P1V design to compile okay for any of their FPGAs, like the ECP5 family for example? I didn't have any luck with getting hold timing met when I tried myself some months back (with the Linux version of Diamond).

    I think we will probably get those FleaFPGA Ohm boards delivered soon. Be real nice to get P1V going for that board but after my earlier battles with the Lattice tools and several days of experimenting I'm now convinced I do not have sufficient FPGA tool experience/knowledge to get all the required the timing constraints specifications figured out to make a P1V meet its clock timing (assuming the ECP5 can get there), and there is no support that I know of - I think Lattice has closed down their forums too. Maybe someone else has had more luck there and understands the timing syntax and issues well enough to have more success than I did...well I hope anyway.

    Once some baseline P1V is working it is much easier to then make all the other changes one may want to do, and a P1V on the FleaFPGA ohm with HDMI and USB would be just about a perfect P1V platform (well for some anyway). I've had way more success with Quartus so far when beginning from a stable design, as would be expected, but I still hope Lattice ECP5 FPGAs and their design tools will ultimately support a P1V.

    Roger.
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