SDRAM chip for P2?

Anybody know what part number makes sense for P2?

I might want to add one to a USB adapter board for A9 P123 board that I'm thinking about...
«1

Comments

  • There's the one that's already soldered on the A9 board (that wasn't on the A7 board). Sounds like a great place to start.

    Not that doing stuff via USB won't be useful, just would probably make sense to get that run ticking over first
  • Wait, there's one already on the A9 board we can use with P2V?

    Never mind then...
  • jmgjmg Posts: 14,567
    edited 2016-05-19 - 20:13:24
    Rayman wrote: »
    Anybody know what part number makes sense for P2?

    I might want to add one to a USB adapter board for A9 P123 board that I'm thinking about...
    Good idea.

    Rayman wrote: »
    Wait, there's one already on the A9 board we can use with P2V?
    Never mind then...

    I think the problem with newer FPGA-kit-included-DRAM, is they are too-new, so are DDR, plus I think these new parts use some PLL scheme, so have clock constraints, and do not like changes in clock speed.

    You probably need to find simpler SDRAM, for P2 ? :

    See the thread by rogloh
    http://forums.parallax.com/discussion/161587/p1v-with-2mb-of-hub-visible-ram-and-now-32mb-of-sdram/p1

    Then there are the new HyperRAM and HyperFLASH parts,
    HyperRAM is in stock at Digikey, and a nice small 25 pin package with a 8 bit bus.

    P2 really should look to supporting this, as the P2 pin count is rather low for SDRAM.
    No one really wants to buy all those smart pins, then lose half of them talking to memory in a large package.

    It would be great to have a PCB where one can connect, to try out the HyperRAM links.
  • cgraceycgracey Posts: 13,176
    edited 2016-05-19 - 21:19:05
    jmg,

    That HyperRAM looks like the way to go. We should have no problem supporting that with the current design. The smart pins can generate transitions on every clock and the streamer can input or output bytes on every clock; hence, the DDR activity.

    HyperRAM only take 8 data + several control signals. This is about 1/3 of what SDRAM requires. That's fantastic!
  • jmgjmg Posts: 14,567
    cgracey wrote: »
    jmg,

    That HyperRAM looks like the way to go. We should have no problem supporting that with the current design. The smart pins can generate transitions on every clock and the streamer can input or output bytes on every clock; hence, the DDR activity.

    HyperRAM only take 8 data + several control signals. This is about 1/3 of what SDRAM requires. That's fantastic!
    Great news to hear it should work - with luck, Rayman will add some to try.

    Yes, it is an ideal fit for P2 - shiploads of RAM or FLASH, and low pin counts.
    Only caveat is BGA, (for now?) but most assemblers can manage that today.

    It is small enough to include on a module, and not make the PCB too large.

  • Can we put RAM and Flash on the same bus?
    Are the pinouts the same?

    Have to look into this...
  • jmgjmg Posts: 14,567
    edited 2016-05-20 - 03:38:02
    Rayman wrote: »
    Can we put RAM and Flash on the same bus?
    Are the pinouts the same?

    Have to look into this...
    I think the bus and pinouts are very similar, and have a /CS, but you might not want to put two parts on one bus, for first testing ?

    The most useful I see as HyperRAM, as there are fast QuadSPI Flash memories out there, but very little in the way of fast SPI SRAM.

    Grab some while they are still in stock ? :)

    If you did want to try XIP, on P2, then you might do 1 x HyperFLASH for Code, and 1 x HyperRAM for Graphics & RAM, on two ports.


    Addit:
    I see 100 x 3V versions are due in a few days, then a longer pause to August for 400 more.

    The Data says this :
    3. CK# is only used on the 1.8V device and is shown as a dashed waveform.
    4. The 3V device uses a single ended clock input.


    some specs may need testing, I see a tCSM max of 1us or 4us ?
    Refresh time are <64ms at 85'C and <16ms at 105'C, but it can auto-refresh while CS is inactive.
  • Two issues.

    1. The last time I looked, to use HyberRam you have to use HyperBus... that's proprietary. I don't know if you get a license with every chip or not:)

    2. Performance... I don't care about the pin count. If I run out of pins, I will add another P2:)

    If HyperRam is just as fast SDRAM, I would keep the pins and pay the royalty.



  • jmgjmg Posts: 14,567
    rjo__ wrote: »
    1. The last time I looked, to use HyberRam you have to use HyperBus... that's proprietary. I don't know if you get a license with every chip or not:)

    The word license appears 0 times in the ISSI HyperRAM document.
    Lots of FPGA will be talking to these, I doubt they try to license those either.

  • rjo__rjo__ Posts: 2,115
    edited 2016-05-20 - 04:30:54
    JMG,

    That's good.

    I came across a discussion about this ... but I don't remember where. That's why I mentioned it.
    I'm too tired to look tonight, I'll try tomorrow. It could be that there is something in the HyperBus documentation
    or is everything in the HyperRam Document? It was a while ago. Could be they changed their minds or I am simply conflating my memory on this... it wouldn't be the first time:)

    Thanks

  • I know that talking to SDRAM isn't simple. And I wouldn't trust myself to fully understand the benchmarks.
    But it does come down to performance. So, this is going to be interesting. I am hoping that when the dust settles, Chip will give us a good SDRAM implementation so we can compare apples to apples.
  • jmgjmg Posts: 14,567
    rjo__ wrote: »
    I am hoping that when the dust settles, Chip will give us a good SDRAM implementation so we can compare apples to apples.

    SDRAM looks trickier to get working than HyperRAM, as SDRAM has RAS.CAS.CS.WRN to all phase right, along with CLK and eg 15 address lines, then data.

    It may work best with 3 Streamers as 4b + 16b + 16b.

    It's not clear from the P2 Specs, if that combination of Streamers is possible ?


    HyperRAM needs an 8b Streamer, with maybe 2 clocks. Fs and Fhr
  • cgraceycgracey Posts: 13,176
    edited 2016-05-20 - 07:28:47
    Having a fast 64MB RAM chip that takes 12 pins, or so, would really be ideal.

    Having huge RAM opens wide doors to being able to do vision processing.

    I've been thinking about all the work that goes on in agriculture and how humans are sorely needed because many decisions have to be made based on subtle cues. Ag doesn't lend it self to automation like Amazon's warehouse. The plants don't conform to grids. There are grids at the macro level, like in an orchard, but each plant is complicated in shape and position - especially all those you DON'T want. There's all kinds of subtlety to what must be pruned, cut, or pulled.

    Here's the thing: We now have good power storage, strong actuators, dirt-cheap cameras, but no brain that can figure out what the heck it's looking at. When that problem gets solved, I think a huge revolution will occur, because then robots will be able to pick right up where humans are. A robot could grab a box of tree tape, some hand cutters, go out to the field and prune and train young trees, with no special tooling or accommodation. It could get a bucket of paint, a brush, a bucket of water, and go paint tree trunks. All day and night. It could keep cutting unwanted weeds away from the trees. It could cut suckers off trees. And the thing is, if several small ones could keep busy with light-duty work, there would never be any heavy work evolving, except maybe the odd tree or broken-limb removal. It's 99% a matter of vision technology coming into capability. That's what's holding up the whole show. It would be fun to work on.
  • Vision recognition is already in widespread use, what with self driving cars, number plate recognition, cctv surveillance everywhere, etc.

    It must work its way down into many other areas, such as your example Chip. All the ducks are in a row. As you say, cameras are as cheap as chips now.

    Video recognition would certainly be fun on a P2. No idea how the algorithms work though.
  • jmgjmg Posts: 14,567
    cgracey wrote: »
    Having a fast 64MB RAM chip that takes 12 pins, or so, would really be ideal.

    Having huge RAM opens wide doors to being able to do vision processing.
    ...

    Comparing SDRAM and HyperRAM, the HyperRAM looks more Streamer compatible, and has Self refresh, but has some unusual data.
    That tCSM of 1 or 4us seems strange, as they also say this

    ["Each individual read or write transaction can use either a wrapped or linear burst sequence... During linear transactions, accesses start at a selected location and continue in a sequential manner until the transaction is terminated when CS# returns High. Linear transactions are generally used for large contiguous
    data transfers such as graphic image moves. "]
    but that low tCSM is less than common line scans ? Needs testing ?

  • If that works out, I might want two of them on Port B...

    Would make double buffering easier...
  • JRetSapDoogJRetSapDoog Posts: 853
    edited 2016-05-20 - 13:15:59
    So that 64Mb HyperRAM part is 8MB, I presume. But I see that their website says "other densities to follow." But even 8MB is a decent amount. Anyway, I dreaded losing half or more of the P2's pins for memory, so I hope this works out. I feel the P2 needs at least 40 pins free after attaching any memory.

    Regarding HyperFLASH, would we be able to add it in to the fractional boot routines as an alternative to SPI? Or would that be too heavy? If possible, a P2 board could use all HyperBUS (RAM/flash) products (and supposedly HyperFLASH is several times faster that quad SPI, though SPI seems plenty fast for booting). Perhaps faster flash would be useful for loading pre-canned fonts and images on-the-fly.
  • Couple problems with HyperRAM PSRAM device:

    There's only one manufacturer.
    Only one supplier?
    The 3.0 V device is not in stock.
    I don't know how to do BGA
  • Vision Processing... thinks like... measure the point spread function for all of the objects in a room. Find all of the mirrors and windows. You can't really reconstruct a scene properly without these assignments and right now these are manual assignments based on guess-taments in post processing. Largely unsolved problems in the real world. The P2 is powerful enough to run multiple algorithms... in parallel... on heterogeneous data... and smart enough to figure out which algorithms to run and which data is best. Consumer cameras can now be controlled over wifi and are getting 1000FPS... Not to worry, we don't need all of the data... just knowing that it is there and that we can eventually tap into it is enough:)

    Rayman,

    Sign me up for 4 of those new boards, HyperRam and all:)







  • I think HyperRAM will have to be a different board (read previous post).

    I'm thinking of making USB board through-hole only so that everybody can solder their own parts on it.
  • T ChapT Chap Posts: 4,049
    edited 2016-05-20 - 20:14:32
    Edit. Nevermind, looks like the product isn't even available(yet).


    http://www.digikey.com/product-detail/en/fairchild-semiconductor/74LCX125MX/74LCX125MXCT-ND/965496

    $0.44 4 i/o 5v tolerant buffer. Not sure how many pins need buffering?

    I think you could solder the BGA by hand. 1mm pitch is not difficult, especially since it is not a lot of pads. There are various methods of applying solder(solder spheres)
  • TubularTubular Posts: 4,217
    edited 2016-05-20 - 14:04:36
    It worries me too Rayman. I did design up a simple breakout but think it'll be a while yet before we could use it. Unless we go 1v8
    There are other part numbers from Spansion eg
    http://www.spansion.com/Support/Datasheets/S27KS_KL-S_PB.pdf

    Perhaps samples are available- that'd be enough for now
  • Glad you found another manufacturer!
    I guess these parts are brand new...
  • I haven't followed closely enough to know the history. But I would have expected parts at digikey/mouser by now. Jmg highlighted these quite some time ago.
  • Tubular wrote: »
    I haven't followed closely enough to know the history. But I would have expected parts at digikey/mouser by now. Jmg highlighted these quite some time ago.

    Slide 6 on the PDF (updated in February) at the following link provides some clues. The HyperRAM looks like it will be in production this quarter. HyperFlash, on the other hand, indicates production, but no expected quarter...

    http://www.cypress.com/product-roadmaps/cypress-flash-memory-roadmap
  • jmgjmg Posts: 14,567
    Seairth wrote: »
    Slide 6 on the PDF (updated in February) at the following link provides some clues. The HyperRAM looks like it will be in production this quarter. HyperFlash, on the other hand, indicates production, but no expected quarter...
    HyperRAM is in stock at Digikey in 1.8v and 3v is next week.
    Rayman wrote: »
    I think HyperRAM will have to be a different board (read previous post).

    I'm thinking of making USB board through-hole only so that everybody can solder their own parts on it.

    Can you put a footprint for HyperRAM on there, so someone can at least try a reflow ?
    If you include an overlay outline to good precision, some edge stops could be stuck on to help locate/

    I've read reports that BGA is not as hard as some imagine, in a reflow setup.
    Pre-tin or pre-paste the PCB ?

  • jmgjmg Posts: 14,567
    Tubular wrote: »
    I haven't followed closely enough to know the history. But I would have expected parts at digikey/mouser by now. Jmg highlighted these quite some time ago.

    It's not just the P2 that has roll-out delays :)

  • RaymanRayman Posts: 11,682
    edited 2016-05-20 - 20:15:51
    I think you need a 4-layer board (at least) to do BGA, right? Can you do it with 2 layers?
    I'll look into it...
  • jmgjmg Posts: 14,567
    Regarding HyperFLASH, would we be able to add it in to the fractional boot routines as an alternative to SPI? Or would that be too heavy?

    It needs 12 pins, so is probably outside the scope of stage one (ROM) boot.

    SPI parts keep falling in price, I see now at Digikey

    SERIAL FLASH 16M-BIT 120MHz TSSOP8 FT25H16T-RB 1,000 $0.13860
    If possible, a P2 board could use all HyperBUS (RAM/flash) products (and supposedly HyperFLASH is several times faster that quad SPI, though SPI seems plenty fast for booting). Perhaps faster flash would be useful for loading pre-canned fonts and images on-the-fly.
    Certainly, I expect boards to use HyperRAM, and then HyperFLASH.
    HyperRAM adds RAM without the massive pin cost, but there are alternatives to HyperFLASH
Sign In or Register to comment.