Prop2 FPGA files!!! - Updated 16 October 2017 - Version 24a

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  • IIRC These results in C are different to the P1.
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
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  • Was just thinking that an "Include" directive for PNut would be useful.
    Would like to combine several text files at compile time...

    I think the "File" directive that is there already is only good for binary data.
    Prop Info and Apps: http://www.rayslogic.com/
  • Rayman wrote: »
    Was just thinking that an "Include" directive for PNut would be useful.
    Would like to combine several text files at compile time...

    There are a great many things missing from PNut, which is why I did some tests with fasmg.

    fasmg is a macro assembler on steroids... looks to be suitable for both P1 and P2
  • Rayman wrote: »
    The BeMicro-A9 seems to have been out of stock for a year.

    I realize I'm a little late to the party, since this comment was made three weeks ago, now.

    Yes, Arrow's BeMicro-A9 development board is out of stock and has been for a long time.
    ( https://www.arrow.com/en/products/bemicrocva9/arrow-development-tools )

    HOWEVER: Out of curiosity, back in early December, I clicked the backorder button and filled out their request form. The response I got back was that if I placed an order for only one, it'd cost me $180 (because they'd be baking-in all of the setup costs into that one board) and I'd be looking at a 14-16 week lead-time.

    I did not order one (yet) as I don't have sufficient time to work on my current mountain of projects, but I thought the quote seemed not unreasonable.
  • melstav wrote: »
    Rayman wrote: »
    The BeMicro-A9 seems to have been out of stock for a year.

    I realize I'm a little late to the party, since this comment was made three weeks ago, now.

    Yes, Arrow's BeMicro-A9 development board is out of stock and has been for a long time.
    ( https://www.arrow.com/en/products/bemicrocva9/arrow-development-tools )

    HOWEVER: Out of curiosity, back in early December, I clicked the backorder button and filled out their request form. The response I got back was that if I placed an order for only one, it'd cost me $180 (because they'd be baking-in all of the setup costs into that one board) and I'd be looking at a 14-16 week lead-time.

    I did not order one (yet) as I don't have sufficient time to work on my current mountain of projects, but I thought the quote seemed not unreasonable.

    Yeah, that's not bad. Parallax is paying $230 per chip, via Digikey, when we build our A9 boards.
  • I just posted a new v15. See first post in this thread.
  • cgracey wrote: »
    I just posted a new v15. See first post in this thread.
    Thanks Chip. :)
    Melbourne, Australia
  • Is REP now N instead of N-1?
    Prop Info and Apps: http://www.rayslogic.com/
  • ozpropdevozpropdev Posts: 1,912
    edited February 1 Vote Up0Vote Down
    All flavours of FPGA images load and run OK with V15.
    Nano, Nano + board, BeMicro A2 & A9, DE2-115, and both P123-A7 and A9. :)

    Edit: Fixed sad face...
    Melbourne, Australia
  • Rayman wrote: »
    Is REP now N instead of N-1?

    Yes, Chip mentioned in the REP issue thread

    I changed the D/# value to be the actual number of instructions to repeat (not # minus 1). If 0 is used for D/#, nothing will be repeated, regardless of the S/# value. PNut.exe has been updated to properly compute #D when @label is used


    Melbourne, Australia
  • Rayman wrote: »
    Is REP now N instead of N-1?

    Yes. My goal is to add REP to the documentation tomorrow.
  • ozpropdev wrote: »
    All flavours of FPGA images load and run OK with V15.
    Nano, Nano + board, BeMicro A2 & A9, DE2-115, and both P123-A7 and A9. :(

    Thanks for checking all those. You've got every FPGA board!
  • RaymanRayman Posts: 8,299
    edited February 1 Vote Up0Vote Down
    These look like the new instructions:
    CCCC 1101011 CZL DDDDDDDDD 001010000   **   FLTL    D/#         {WC,WZ}
    CCCC 1101011 CZL DDDDDDDDD 001010001   **   FLTH    D/#         {WC,WZ}
    CCCC 1101011 CZL DDDDDDDDD 001010010   **   FLTC    D/#         {WC,WZ}
    CCCC 1101011 CZL DDDDDDDDD 001010011   **   FLTNC   D/#         {WC,WZ}
    CCCC 1101011 CZL DDDDDDDDD 001010100   **   FLTZ    D/#         {WC,WZ}
    CCCC 1101011 CZL DDDDDDDDD 001010101   **   FLTNZ   D/#         {WC,WZ}
    CCCC 1101011 CZL DDDDDDDDD 001010110   **   FLTN    D/#         {WC,WZ}
    CCCC 1101011 CZL DDDDDDDDD 001010111   **   FLTIN   D/#         {WC,WZ}
    
    CCCC 1101011 CZL DDDDDDDDD 001011000   **   DRVL    D/#         {WC,WZ}
    CCCC 1101011 CZL DDDDDDDDD 001011001   **   DRVH    D/#         {WC,WZ}
    CCCC 1101011 CZL DDDDDDDDD 001011010   **   DRVC    D/#         {WC,WZ}
    CCCC 1101011 CZL DDDDDDDDD 001011011   **   DRVNC   D/#         {WC,WZ}
    CCCC 1101011 CZL DDDDDDDDD 001011100   **   DRVZ    D/#         {WC,WZ}
    CCCC 1101011 CZL DDDDDDDDD 001011101   **   DRVNZ   D/#         {WC,WZ}
    CCCC 1101011 CZL DDDDDDDDD 001011110   **   DRVN    D/#         {WC,WZ}
    CCCC 1101011 CZL DDDDDDDDD 001011111   **   DRVIN   D/#         {WC,WZ}
    

    So, looks like FLT is for float and DRV is for drive.
    Guess the C,NC,Z,NZ affect the out bit, just like L for low and H for High.

    What do the "N" and "IN" stand for?

    Also, I think you said before that the IN gets sampled before DIR is changed, right?
    Prop Info and Apps: http://www.rayslogic.com/
  • Rayman wrote: »
    Was just thinking that an "Include" directive for PNut would be useful.
    Would like to combine several text files at compile time...

    I think the "File" directive that is there already is only good for binary data.

    I am still away from home. So, I can't experiment right now.
    I have used the File directive to include precompiled code and got it to run as code.

    I don't think PNUT cares what kind of file it is... I have use my own "file type" designation for both 24 and 32 bit data.
    I think as long as you are loading an ascii text file into Hub Ram, you should be fine. You would need an interpreter to use the text,
    but that should be fairly straight forward.



  • I'd like to have a text file with ascii source code in it to be included into the source code.
    It would just be a nice thing, don't need it.
    Prop Info and Apps: http://www.rayslogic.com/
  • Rayman wrote: »
    I'd like to have a text file with ascii source code in it to be included into the source code.
    It would just be a nice thing, don't need it.

    Yes, Include files, along with Conditional Assemble, and Macros, are pretty much 'standard features' in any MCU assembler design flow.

  • Rayman wrote: »
    What do the "N" and "IN" stand for?

    The N is for NOT like in OUTN and DIRN and toggles the current state.

    Melbourne, Australia
  • Thanks. Looks like the IN ones do nothing with OUT.
    Think I'd call them plain "DRV" and "FLT"...
    Prop Info and Apps: http://www.rayslogic.com/
  • Roy ElthamRoy Eltham Posts: 2,147
    edited February 1 Vote Up0Vote Down
    jmg wrote: »
    Rayman wrote: »
    I'd like to have a text file with ascii source code in it to be included into the source code.
    It would just be a nice thing, don't need it.

    Yes, Include files, along with Conditional Assemble, and Macros, are pretty much 'standard features' in any MCU assembler design flow.
    C style preprocessor available in OpenSpin for Prop 1. Can't do macros really, but has include and conditional stuff.

  • cgraceycgracey Posts: 8,009
    edited February 5 Vote Up0Vote Down
    I made a Google Sheet with the instructions set on it. You can sort by various columns by clicking the little box within the letter designators at the top of the sheet:

    https://docs.google.com/spreadsheets/d/1EM9LYoqcUgn0hAhzE38vLEi7-IABeD1CdLqDgICx3Hc/edit?usp=sharing

    Next week, I'll fill in the meat on the rightmost column. Then, in the doc's, I'll just explain the outlier things like REP in detail.

    I did a lot of timing checks to get the timing data straight. I can't understand why RETA/RETB takes 20...65 clocks in hub-exec mode! I'll look more into that on Monday.

    Meanwhile, Here's the timing tester program I used to measure everything. It's set up for RETA/RETB in hub-exec:
    dat
    		org	$100
    
    shortest	res	1
    longest		res	1
    x		res	1
    y		res	1
    z		res	1
    j		res	1
    
    		org
    
    		jmp	#main
    
    		orgh	$400			'hub exec
    
    main		mov	shortest,#100
    		mov	longest,#0
    
    loop
    
    	getrnd	ptrb
    	and	ptrb,#$FF
    	pushb	##nxt
    
    		getrnd	x			'random wait to offset hub timing
    		and	x,#$FF
    		waitx	x
    
    		add	z,#1			'incremental wait to kill patterns
    		and	z,#$FF
    		waitx	z
    
    		getct	x			'get initial time
    
    	retb				'instruction to time goes here
    
    nxt		getct	y			'get terminal time
    
    		sub	y,x			'get difference
    		sub	y,#2			'subtract out GETCT time
    		max	shortest,y		'update shortest time
    		min	longest,y		'update longest time
    
    		setbyte	outa,shortest,#0	'write shortest time to P7..P0
    		setbyte	outa,longest,#1		'write longest time to P15..P8
    		mov	dira,##$FFFF		'make pins P15..P0 output
    
    		jmp	#loop			'do another timing
    
  • SeairthSeairth Posts: 2,228
    edited February 5 Vote Up0Vote Down
    PUSHB? nevermind. I see what you are doing, now. Is that instruction an alias? It's not in your spreadsheet.
  • Seairth wrote: »
    PUSHB? nevermind. I see what you are doing, now. Is that instruction an alias? It's not in your spreadsheet.

    PUSHB is an alias for 'WRLONG D,PTRB++'.
  • I always feel like D and S are backwards for WRLONG...
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  • RETA has to do a rdlong to get the address to jump to and then has to read instructions to jump to if that address is in hub, right? I can see that taking a while...

    If the return address is in cog ram, maybe that's the 20 clock case?
    Prop Info and Apps: http://www.rayslogic.com/
  • Rayman wrote: »
    I always feel like D and S are backwards for WRLONG...
    When using hub instructions I think in terms of data & address rather than dest and source.
    RDLONG data,address
    WRLONG data,address
    
    Same for LUT instructions too.
    Melbourne, Australia
  • We're any of you that looked at the instruction spreadsheet able to sort the rows by column (A-Z, for example)?
  • cgracey wrote: »
    We're any of you that looked at the instruction spreadsheet able to sort the rows by column (A-Z, for example)?
    Yes, works just fine!

    -Mike R...


  • cgracey wrote: »
    We're any of you that looked at the instruction spreadsheet able to sort the rows by column (A-Z, for example)?

    I was able to sort by columns AFTER I clicked on "DATA/Sort by column".
  • pmrobertpmrobert Posts: 412
    edited February 6 Vote Up0Vote Down
    DaveJenson wrote: »
    cgracey wrote: »
    We're any of you that looked at the instruction spreadsheet able to sort the rows by column (A-Z, for example)?

    I was able to sort by columns AFTER I clicked on "DATA/Sort by column".
    Dave, as well as that approach, if you hover over the column ID a small down arrow icon will appear that, upon clicking, allows you to sort A-Z, Z-A or "Get link to this range". It's not very obvious for sure...

    Mike R...

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