Custom P1 Verilog code generator
ozpropdev
Posts: 2,791
Hi All
This is a tool for generating Verilog code for a P1V based on the configuration set by the user.
It uses Chip's "master" Verilog files as the base code and makes the necessary changes to it to accommodate the options needed.
All changes are marked in the cod e bu a "<=-" marker with a reason for the change.
The tool can load modified .binary images from Propeller Tool to allow modification of the rom contents.
Here's an example of the commands needed to build a custom P1 with 4 cogs, 3 counters per cog, PortB added, no video and 60K hub ram.
The target FPGA is a BeMicro CV in this example.
It's a little "rough" around the edges but served me well in getting the Max10 P1 up and running.
I'm putting some notes together on using Quartus II and it quirks (there's a few).
Feel free to quiz me on any aspect of the tool as documentation is not my strongest skill.
Cheers
Brian
Latest version 0.21 16th April 2015
See here
This is a tool for generating Verilog code for a P1V based on the configuration set by the user.
It uses Chip's "master" Verilog files as the base code and makes the necessary changes to it to accommodate the options needed.
All changes are marked in the cod e bu a "<=-" marker with a reason for the change.
The tool can load modified .binary images from Propeller Tool to allow modification of the rom contents.
Here's an example of the commands needed to build a custom P1 with 4 cogs, 3 counters per cog, PortB added, no video and 60K hub ram.
The target FPGA is a BeMicro CV in this example.
>new >target cv >video - >portb + >cogs 4 >ctr 3 >hub 60 >dest c:\p1_fpga\test >rom myrom >build
It's a little "rough" around the edges but served me well in getting the Max10 P1 up and running.
I'm putting some notes together on using Quartus II and it quirks (there's a few).
Feel free to quiz me on any aspect of the tool as documentation is not my strongest skill.
Cheers
Brian
Latest version 0.21 16th April 2015
See here
Comments
I think I just worked out what to do with my long weekend..
This looks like a lot of fun!
To think I just got a BEMicro MAX10 to test it out on! I think I just figured out why my weekend got shorter.....
I just updated the docs to include the PLL multiplier/divider commands.
A correction was also made to the MAKEROM command.
Really nice.
Just got back from vacation and couldn't wait to try it out. The instructions are very clear. Everything installs and runs first time:)
When using "portb +", the dig.inc file doesn't get generated.
Also, in your instructions, I think you should mention setting the project to SystemVerilog.
One of the most confusing aspects for a newcomer is pin assignments... For example getting the P1v onto Parallax's de2-115 adapter was a major pain. So... having this as command option would be sweet.
I've also grown very fond of using .bsf files... so having the option to generate a symbolic version of the project would also whittle away the learning curve and let a newbie concentrate on more interesting issues first.
Thank you!
Rich
I forgot to mention the dig.inc file generation procedure in the docs.
It can be done by Quartus by opening the dig.v file and then doing the following from the menu.
File - Create/Update - Create AHDL include files for the current file.
I am currently tweaking the code to enhance it a bit. 'll add the dig.inc file generation too.
On the subject of pin assignment that's what I am currently working on at the moment.
The idea is to avoid using Quarus's clunky schematic editor and speed things up a lot.
Fore example a target associated file is loaded with all the "toys" of the target board.
To add a LED to your project you would simply do one of the following variants Some other assorted associated commands for removing,moving,swapping and compacting pins are also in the mix.
A new command generates a .qsf pin assignment file and another command generates a .spin CON block with all the definitions used in the project.
I hope to have this all done by the end of the week.
Cheers
Brian
You make me smile from ear to ear. Have some coffee:)
Rich
I'm just finishing up some testing on the revised version of the Verilog code generator.
I got caught up in trying to get more than 8 cogs. Temporarily skipped that for the moment
and will come back to that later.
So here's some of the additions.
Support for larger hub memory models >64k.
Pin assignment tools to rapidly generate qsf files for Quatus.
Asymmetrical cog support. (Mixed features per cog i.e. Video, Counters, Ports, ALU)
and lots of little tweaks to operation.
Hope to have the associated documentation done in the next day or two.
What were your problems with trying more than 8 cog?
Status indicated that 8 cogs were built and the extra 8 were "synthesized away".
The generate loop and all associated regs and buses in all associated .v files were expanded for the 16 cogs.
It seems to be associated with missing clocks, but not 100% sure yet.
Spent a huge amount of time on it with no results. I will come back to it though.
Here's the latest version of p1v_toolbox.
What's new!
Cogs can now be asymmetrical. Functions can be enabled/disabled per cog. i.e. video, counters, ports
2 additional ports can be included now PortC and PortD for up to 128 I/O.
Larger hub memory support (>64k) i.e. 128,256,512k depending on target.
A quick pin assignment demo for a Nano board
This will create a project in c:\p1_fpga\demo1.
A single pushbutton attached to pa0
Eight leds attached to pa8 to pa15
Propplug is assigned by default.
All relevant Verilog files (*.v, *.inc, *.tdf) ,pin assignment files (*.qsf) and a .spin file with clock and pin info.
Create a new project in Quartus using the new toop.tdf file in the new folder.
Import the pin assignments from the file demo1.qsf
Use the device part number in the top.tdf file to set the device.
Remember to select System Verilog in the settings.
I think I've got the new commands covered in the docs. Apologies in advance if I'm unclear.
Feel free to quiz me on any aspect of the tool.
Have fun!
Correction: Changed to 1 pushbutton from 2. Only 1 PB can be used on DE0-Nano
I cannot wait to try it out, hopefully later today
Very impressive, some really nice touches such as the MHZ selector that shows nearby ratios, and the MAP memory visualization command that shows the memory map clearly, and VIEW for the cog setup.
Really well done... if you're able to run windows code this is well worth checking out
The standard P1 booter refers to address FFF9FFFF for the propeller version number. The rom/ram decode usually "rolls over" so any access to addresses with the lower 16 bits
set will normally return a 01 byte or the version number set by p1v_toolbox.
The same applies to spin's "CHIPVER" function.
With larger hub ram the decoding is modified to accommodate the larger address space.
Because of this change then version number returned will always be 0.
This is not a problem for Propeller Tool but causes issues with PropellerIDE.
In PropellerIDE if the com port is set for "AUTO" the IDE does not detect a propeller.
If using p1load.exe set the com port to your known com port and PropellerIDE will download to the propeller
even though a "Identify Hardware" wont find the propeller.
If using propellerloader.exe it doesn't seem to like a 0 version number at all.
Here's a simple fix if it's a problem. In booter.spin make the following changes.
ver_addr long $ffff rdbyte bits,ver_addr 'get version byte at $FFFFIn Propeller Tool add a dummy PUB so it can compile the source and save as a .binary file.
In p1v_toolbox use the loadbin command to load the rom image then use makerom or savehex to
create a .hex file for use in your p1v.
What I don"t understand yet is the pin assignment thing. I made a P1Voz with ports B,C and D enabled, do see correct Verilog code, but no pin assignments. Do I have to add that manually in the Quartus pin editor, or in the toys???
In Quartus you need to import the pin assignments. From the menu >Assignments>Import Assignments..
Make sure the device and device family are correct in the "Device" dialog.
To verify the correct device is set use the >Assignments>Pin Planner functiom. You should see a top view of the device.
After a "import" you will need to set the compiler for "Verilog HDL Input" to "System Verilog"
In "Synthesis" settings make sure you also set "Block Design Naming" to" Quartus II".
If you created a project called "p1voz" there should be a file called "p1voz.qsf".
Check that this file contains the pin assignments you set. Let me know if it doesn't and I will check it further.
Hope this helps
Had a couple of hiccups on install as I didn't put the files where you wanted originally. Done that now.
Quick try with Quartus but no go. Didn't have time to see what didn't work. Maybe tomorrow.
BTW I am on Windows 8.1 64bit. When downloading from the forum with IE it loses the download filename - get attachment.php but its all there when I rename it xxx.zip and xxx.txt. Bad windoze.
I get the same attachment.php issue with everything I download from the forum. Running Win 7 32 bit and IE11.
I can't remember NOT having this download issue. A rename seems to work though.
These pins when assigned to P1V's bi-directional ports conflict and cause comile errors.
So KEY1 and the DIPSW0..3 cannot be assigned for use with a P1V.
I will check and see if we miss out on other toys on the DE2-115,DE0-CV,BeMicro CV & BeMicro Max10.
Just delete these items from the nano.toys file.
I realised you have a hub memory in the pc to represent the hub.
So I have loaded up the hub rom section with what I want and have used dump to verify.
When I went to save the resultant hex file it failed. After a few trials and errors I realised p1v_toolbox requires the file to pre-exist so it can overwrite the file.
BTW this saves me a lot of work. Previously I have been using spin to save hex files from hub.
Congratulations Brian.
If possible, I would love a simple command to store a byte into the hub ram/rom.
It doesn't need to be complex as I don't intend to do much.
It would be easier than editing a hex file and recalculate the checksum.
BTW I am currently trying to reorganise hub rom $F004..FFFF to fit in my vector table.
I just added a byte entry command to the mix. It should do the trick!
Cheers
Brian
I will give it a go in the morning.
Then run setup.exe from c:\p1_fpga
BTW there is nothing displayed as/after it runs (after I give windoze the ok to run)
It seems to always bring up v0.2 and not the new v021
any ideas?
From the "Apps" screen I did a uninstall first of p1v_toolbox (Right click p1v_toolbox to select uninstall)
This will take you to the "Programs and features" dialog. Scroll down to p1v_toolbox and right click on it to uninstall.
I then double clicked the zip file and select "Extract" from the dialog box and then "Extract all".
Using the "Browse" function to select the existing "c:\p1_fpga" folder.
Then clicked "Extract" and agreed to replace files.
Then ran setup from c:\p1_fpga and p1v_toolbox installs and starts.
Btw dislike windoze 8.1. Even finding a new installed program is a chore.
I have calculated if I break runner into 3 sections, I can fit my 254 long vector table
Into $FBF8..FFF7. I have worked how to split runner
I set up a couple users with that one, and they are fine.