The DE2-115 has a Cyclone IV 4CE115 which has 115K LEs.
The Cyclone V 5CEFA7C8N has 150K LEs. I might expect that this may in fact hold the full 8 cog design because currently we seem to be at ~25K (it doesn't fit the 22K DE0) but this has much of the hub logic too. The FPGA chip alone is ~$180 from DigiKey.
I don't want to be negative but I must say how difficult I think it will be to create a fpga developer community with such high prices.
Minimal FPGA boards (like DE0-nano or BeMicro CV) are wonderful pieces of hardware. DE0-nano has proved to be useful. It just only lacks more logic elements.
Why don't just make something similar to this boards but with a bigger FPGA like Cyclone V A7?
If Parallax has such high NRE cost, why not ask Terasic or Arrow for a DE0-nano / BeMicro CV customized board?
Sure, it will be difficult and you are totally correct. Designing chips is also difficult, but we're doing that too. There are always easier ways to make a living, but could it possibly be as interesting as this? Not a chance! With the community we have in you and everybody else, we're going to achieve this goal without question.
We have some reasoning behind our plans to use a big FPGA that can run nearly the whole P2 design but I can't disclose every single piece of our plan at this stage. Also, it's about features. We need a board that we can use for Propeller 1, 2 and 3. You're going to want the same board, so we'll design the one that lets us do all of these things, with enough interesting I/O facilities that you can design a product in advance of having the chip.
Asking Terasic for support isn't of interest. While they are perfectly capable, it would happen slower, at a higher cost, and with lots of communication overhead.
We have some reasoning behind our plans to use a big FPGA that can run nearly the whole P2 design but I can't disclose every single piece of our plan at this stage.
Intriguing! Any idea when you'll be ready to let us in on the secret?
With a Parallax FPGA board, you can get your code working before the P2 is available. Then you can debug your code, and I mean with tracing etc when we get Chip to add some more debugging features to the FPGA code. Some really smart debugging can be done this way with a little extra Verilog code. No need for this to be in silicon.
Suppose you have a project that is going to use lots of P2s but you just need that little bit extra - you pay Parallax to add that feature, you test it out on the FPGA, then order x,000's of your own custom chips. Bet this would be cheaper than your own ASIC !
Now, where did I place that nano-bug fly replica to bug Kens office
I think the growth rate of Logic Elements needs to be allowed for, and if this is done both the DE0 Nano and BeMicro CV (A2 cyclone V) won't take us where we all want to go, for very long
A bit over a year ago a full cog fitted in something like 80% of a DE0 Nano - lets say 18k LEs. As of last release we only get 4 cogs in a DE2-115 (23k-28k LEs/cog?) There's a distinct possibility we wouldn't fit in a BeMicro *now*, let alone after the next release from Chip, let alone whatever we're testing by the time production silicon arrives.
With A7, We should be able to run at least two P3 cogs if they are < 75k LEs each, so plenty of room to grow into. P3 will likely need more i/o pins too and DDRx memory support and these combined features can be accommodated readily by going the Parallax A7 path. Plus if these cyclone V's are pin compatible parallax have the option to load smaller FPGAs to get more developers/testers onboard.
A bit over a year ago a full cog fitted in something like 80% of a DE0 Nano - lets say 18k LEs. As of last release we only get 4 cogs in a DE2-115 (23k-28k LEs/cog?) There's a distinct possibility we wouldn't fit in a BeMicro *now*, let alone after the next release from Chip, let alone whatever we're testing by the time production silicon arrives.
True, it is a moving target.
However there are Cyclone V's in steps, of 25k, 49k, 77k, 149.5k, 301k LE's
Some of these have vertical migration, so it is not a large step to release another development board.
The 49k part, is under $60, and should support a single COG logic, past where it will no longer fit in the package.
Parallax may even be able to offer more than one assembly option, mounting different sizes Cyclone V.
I think the growth rate of Logic Elements needs to be allowed for, and if this is done both the DE0 Nano and BeMicro CV (A2 cyclone V) won't take us where we all want to go, for very long
A bit over a year ago a full cog fitted in something like 80% of a DE0 Nano - lets say 18k LEs. As of last release we only get 4 cogs in a DE2-115 (23k-28k LEs/cog?) There's a distinct possibility we wouldn't fit in a BeMicro *now*, let alone after the next release from Chip, let alone whatever we're testing by the time production silicon arrives.
With A7, We should be able to run at least two P3 cogs if they are < 75k LEs each, so plenty of room to grow into. P3 will likely need more i/o pins too and DDRx memory support and these combined features can be accommodated readily by going the Parallax A7 path. Plus if these cyclone V's are pin compatible parallax have the option to load smaller FPGAs to get more developers/testers onboard.
The A7 & A9 basically share common pins, and the A2, A4 & A5 basically share common pins, but without looking closely, the datasheets say they do NOT share common pinouts between these sets. The A9 is another $50 and has 300K LEs.
From what I understand, the Cyclone V has better routing than the IV and the LEs are more powerful. So potentially there are some gains to be had with the V family.
The A7 & A9 basically share common pins, and the A2, A4 & A5 basically share common pins, but without looking closely, the datasheets say they do NOT share common pinouts between these sets. The A9 is another $50 and has 300K LEs.
From what I understand, the Cyclone V has better routing than the IV and the LEs are more powerful. So potentially there are some gains to be had with the V family.
We would certainly opt for the -A9, but it doesn't work with free Quartus Web Edition. You'd need to buy the $3k/year licensed version to compile for that part.
Those prices are significant. After thinking about it, I would rather make the investment in a board that will work for a while, and I want to get to a point where I'm learning about the FPGA, not just the chip design going on with it. --which means potentially having a cheap compile part to work on in tandem. You guys should think about that. I know I can't do 3K to learn, but I can do a few hundred to run compiled code, test, and a few more to have a board I can write for.
This means being able to run a reasonable chunk of a P3 on the primary board. Given a successful, and potentially customizable P2, that project is likely to be very interesting!
And that means I'll figure out how to fund the Parallax board, and a significant chunk of it's value will be "center of gravity" on these efforts. Having a lot of different FPGA platforms out there will dilute and complicate things. This is undesirable, and frankly the appeal of this whole thing is either worth some personal investment, or it's not. Simple numbers aren't meaningful in the same sense as they are for chips. Some investment will qualify participants and I think we need that.
(I'll likely do some contract work on weekends to get the thing paid for, if nothing else)
Having applied that logic to the DE2, I'm pleased with the result.
Down deep, I'm kind of hoping we can get to some, "design it, test it, get it made in silicon model" because it aligns very well with the growing "maker" movement, and it aligns very well with the many complex, highly specialized, often non-accessible devices out there. I look at the spec sheets, block diagrams, dev kits, and I see a lot of convergence on the same sets of ideas with some variations bolted on here and there. It's a mess!
Better targeted and accessible silicon is a growing niche. I also believe, and have been researching, products in general, and better, well targeted products are also on the rise and a lot of the differentiation falls along the lines of user interaction and enabling / supporting hardware required. Typically, this means crude user interfaces, or the need for a PC / Tablet, etc... which complicate things, and most importantly, link it to that "octopus" Chip mentions from time to time.
BTW: Things like the onboard video, tasks (and yes that's complicated, but once sorted out, baked in, no OS octopus required), smart I/O pins, lots of DAC, counters, SERDES, etc... that makes reaching for superior user interaction viable! Right now, on Android, latency is a PITA. And in mobile, there is a big divide over how Apple does it, no garbage collection, code review, testing, power management as a primary thought in libraries, etc... and the Droid model, which is more sloppy. Each have their trade-offs, and the Apple devices typically have the best user interaction and overall design, but they are often a PITA to develop for and Apple themselves has to review and test in ways many find toxic, however good the end result is. On the Droid end of things, just about anybody can jump in, but then the cost is a less robust overall experience, and fragmentation of sorts. Also, latency. Sometimes lots of it. I'm not a fan of that aspect of Droid so far. Frankly, I've not found a low latency UX experience on Droid yet. I'm sure it's out there, and I'm sure they worked their arses off for it too...
Secondly, platforms are being shrunk down right now in an attempt to get at this smart device movement, and the problem is all the legacy baggage being carried forward, need for complex OS / kernel software, drivers, and other things all tend to dilute the value down, while fragmentation and differentiation remain tepid for the same kinds of reasons. The idea that we might have a basic platform on a chip is very compelling when weighed against these kinds of offerings, and we could use external RAM and some devices, or next to nothing but the essentials depending on product scope and the overall path to development and design would be remarkably similar, with high reuse potential. Of course, the highest reuse will depend on open code, and with the protection in the chip now, I really don't know how that will shake out. Hoping for goodness there.
What I've come to realize is there are a lot of great ideas out there. Many of them have seen the light of day too, but they never did reach a critical mass, so they remain in niche land, or simply not used much at all. That no branch, time slice, no loop control system Heater mentioned, is typical of these ideas that pack a punch, but do not relate to the largely homogenous silicon out there today.
The basic ideas in the P2 are distinctive, and one artifact of that is the ability to make something that has a superior user interaction model while performing well without requiring an operating system or other complex, or linked to "the octopus" software being involved.
Just recently, Ford announced a switch to QNX in it's vehicles, away from Windows! (The Ford I have is pre-Windows, thankfully.) If one were to extrapolate some, take a few lessons from ARM, etc... it doesn't take too much to realize a "Linux" in silicon may well develop quite a following for it's lean development model, perhaps on chip where warranted / desired, high performance and interactivity. That means platform on a chip, more than it means, make a cheap board, IMHO.
Where BOM costs are considered, think about this! Apple generates a BOM similar to it's peers. Now, don't get me wrong, they are smart and they do get that BOM cost down through smart sourcing, design, etc... This is notable, and others do it too. What is notable is the margins they can get for devices that offer both a very superior user interaction model, and some basic smarts built in. Nest labs is another example of this, with simple utility devices being made smart, and extremely high value. Nobody employing that model moves as many devices, but they capture margins worth doing, and most importantly, those margins are enough to fund further development, not races to the bottom.
It is these kinds of things that make the "can we work together and get to silicon?" effort seen here appear particularly compelling on a number of fronts well beyond having a successor to P1.
(we shall see how close to the mark some of that is in due time, won't we Ken? )
re: We need a board that we can use for Propeller 1, 2 and 3
Speaking of Prop 3 , is there any chance you can release that one now because they are still adding features to Propeller 2 and it' going to be a while.
We would certainly opt for the -A9, but it doesn't work with free Quartus Web Edition. You'd need to buy the $3k/year licensed version to compile for that part.
Ouch! What a gouge. It is not as if you can use their software on someone elses FPGA. And I do recall you mentioning this some time ago.
I was quite happy with the A7, but now there are 3,000 more reasons per year
Ok, "the community" is challenging and second guessing the design of a board that is trying to be released quickly to help us test the chip that has been under constant redesign since September.
The A7 would be a good choice. If we need a 3 k$/y licence then we can also afford Altera's own boards for these devices. We will be out of the equation.... (you could provide some custom encrypted IP with a P2 inside, no idea whatsoever how that can be done, but it is possible).
One COG has grown to ~24 000 LEs, those are some +2,000,000 gates?!. Don't get me wrong the features are amazing but "simple" cannot be used anymore to describe it. in an A7 can we fit 4 COGs, 4 threads each... not too shabby !... The P3 would be probably 4 times that... Than it may be better to choose whatever is affordable and big enough at the time the design is mature enough for our consumption...
Ok, "the community" is challenging and second guessing the design of a board that is trying to be released quickly to help us test the chip that has been under constant redesign since September.
Parallax may even be able to offer more than one assembly option, mounting different sizes Cyclone V.
Several FPGA development boards has a small square board that holds the FPGA, flash memory, RAM, and voltage regulators only; and a second board that has IO connections.
I think this is a good idea. There are two good reasons to do this. The first is that the FPGA could be used for other projects or purposes. The second one is that it can be upgraded. Who knows if Altera would include Cyclone V A9 (or any other big FPGA) inside the free quartus edition in the future.
Ken, thanks for your comments, I understand and agree that Parallax needs its own board. I hope you could get a big discount for those 1,000 FPGAs. Digikey and mouser only shows the price for 1 unit. And Altera website also doesn't show any discount for multiple units. Also I have noticed in Altera's website that they don't have enough FPGAs in stock. They just show around 100 pieces maximum for just three or four models (all A7). The delivery time for more quantity than this is around the end of april.
We would certainly opt for the -A9, but it doesn't work with free Quartus Web Edition. You'd need to buy the $3k/year licensed version to compile for that part.
What about loading pre-compiled code to A9 (ie just loading a binary blob) - does that also need the $3k licensed version?
What about loading pre-compiled code to A9 (ie just loading a binary blob) - does that also need the $3k licensed version?
Probably not but I thought the idea was to get forum members involved with actually writing Verilog for P3. Anyone who wants to compile Verilog would need the $3K license.
What about loading pre-compiled code to A9 (ie just loading a binary blob) - does that also need the $3k licensed version?
That could make sense, depends on the BGA reflow flows I guess.
If the package is the same, it becomes an order-tracking exercise at Assembly time.
Do Parallax have experience internally in BGA package place+soldering, or is this a contract run ?
That suggests the 484 pin version has coverage over all die A2..A9, to 224 io lines
I'm not sure on the costs of the companion Loader-Flash, but if that is significant a paired-build of Flash+FPGA could make sense.
Probably not but I thought the idea was to get forum members involved with actually writing Verilog for P3. Anyone who wants to compile Verilog would need the $3K license.
Long term yes, but someone who wants to use all 8 COGs of a P2, may be fine with pre-compiled files for a time.
A rough calc on A9 gives 301k/8 = 37.6k LE per COG ceiling.
With no numbers seen yet for a Cyclone V build, the exact LE usage may be lower than for Cyclone IV.
Long term yes, but someone who wants to use all 8 COGs of a P2, may be fine with pre-compiled files for a time.
A rough calc on A9 gives 301k/8 = 37.6k LE per COG ceiling.
With no numbers seen yet for a Cyclone V build, the exact LE usage may be lower than for Cyclone IV.
Yes but if Parallax uses the A9 chip then whoever buys it will never be able to contribute to the Verilog code even later down the road. Maybe the idea of a plug in module with the FPGA on it should be considered so someone could have a base module with both an A7 and an A9 FPGA module? I guess that probably wouldn't be that good an idea though since the FPGA is the most expensive part and a second FPGA module might cost almost as much as a complete second board. It's too bad that Altera doesn't limit the size of the design rather than the size of the FPGA.
with 77k LE's it should fit 2-3 cogs easily, and it has enough I/O on board that it would not need an expansion module (24bpp VGA, uSD, etc)
Even at the full $200 price it will be half the cost of the really nice 150k LE parallax board, and let a lot more people in on the fun with p2/p3
While I hope the DE0-Nano will still be supported (missing some features) I think we need another "lower end" emulation platform, and $150-$200 for the De1-SoC is an excellent low/mid range choice.
I'd still like to see support for the De1-Soc
..
Even at the full $200 price it will be half the cost of the really nice 150k LE parallax board, and let a lot more people in on the fun with p2/p3
Yes, ideally, a choice of target builds will be available, for the other Cyclone V price point boards out there.
We still do not know if the very affordable BeMicro will fit a COG, as there are no Cyclone V build stats I've seen yet.
Altera do show 2 parts (25k & 49k) in the smallest package vertical migration, so that means a larger "BeMicro Plus" may just be a build decision away.
It would cost us about $5K to make 25 boards, even though the BOM cost is near nothing. The cost is all labor, all the time: buyers, inventory planners, engineers, all have their fixed role in anything we do, regardless of volume. Daniel is already behind schedule with or FPGA board so I don't want to add to the delay.
I have a DE0 that has been without a breakout board since I bought it in July, so I've been without video since then. Puts quite a damper on my fun. But I am anxiously anticipating the Parallax Cyclone V board and will be purchasing one as soon as they are available, so considering the crazy cost of such a small run I can't see how it makes sense to do it. Even more important is to not spend the time on such a thing. But if anyone has an old, unused DE0 board they can part with, I'd certainly appreciate it!
What about loading pre-compiled code to A9 (ie just loading a binary blob) - does that also need the $3k licensed version?
No. That could be done for free, but it would exclude forum members from being able to compile the Verilog themselves and try out new ideas of their own.
I have a DE0 that has been without a breakout board since I bought it in July, so I've been without video since then. Puts quite a damper on my fun. But I am anxiously anticipating the Parallax Cyclone V board and will be purchasing one as soon as they are available, so considering the crazy cost of such a small run I can't see how it makes sense to do it. Even more important is to not spend the time on such a thing. But if anyone has an old, unused DE0 board they can part with, I'd certainly appreciate it!
Bart,
Check out post#51 above. Have I got a deal for you!!
Comments
That even depends on on chip RAM
Sure, it will be difficult and you are totally correct. Designing chips is also difficult, but we're doing that too. There are always easier ways to make a living, but could it possibly be as interesting as this? Not a chance! With the community we have in you and everybody else, we're going to achieve this goal without question.
We have some reasoning behind our plans to use a big FPGA that can run nearly the whole P2 design but I can't disclose every single piece of our plan at this stage. Also, it's about features. We need a board that we can use for Propeller 1, 2 and 3. You're going to want the same board, so we'll design the one that lets us do all of these things, with enough interesting I/O facilities that you can design a product in advance of having the chip.
Asking Terasic for support isn't of interest. While they are perfectly capable, it would happen slower, at a higher cost, and with lots of communication overhead.
Ken Gracey
Intrigued? You'll have to go to the early adopters conference in May/June where all will be revealed.
Sounds like a great way to boost attendance
(I'm intrigued too and may make the trip...)
So the BeMicro CV and the upcoming DE1-SoC Board can slot in under the Parallax Board at differing GOG/Cost points.
With a Parallax FPGA board, you can get your code working before the P2 is available. Then you can debug your code, and I mean with tracing etc when we get Chip to add some more debugging features to the FPGA code. Some really smart debugging can be done this way with a little extra Verilog code. No need for this to be in silicon.
Suppose you have a project that is going to use lots of P2s but you just need that little bit extra - you pay Parallax to add that feature, you test it out on the FPGA, then order x,000's of your own custom chips. Bet this would be cheaper than your own ASIC !
Now, where did I place that nano-bug fly replica to bug Kens office
A bit over a year ago a full cog fitted in something like 80% of a DE0 Nano - lets say 18k LEs. As of last release we only get 4 cogs in a DE2-115 (23k-28k LEs/cog?) There's a distinct possibility we wouldn't fit in a BeMicro *now*, let alone after the next release from Chip, let alone whatever we're testing by the time production silicon arrives.
With A7, We should be able to run at least two P3 cogs if they are < 75k LEs each, so plenty of room to grow into. P3 will likely need more i/o pins too and DDRx memory support and these combined features can be accommodated readily by going the Parallax A7 path. Plus if these cyclone V's are pin compatible parallax have the option to load smaller FPGAs to get more developers/testers onboard.
True, it is a moving target.
However there are Cyclone V's in steps, of 25k, 49k, 77k, 149.5k, 301k LE's
Some of these have vertical migration, so it is not a large step to release another development board.
The 49k part, is under $60, and should support a single COG logic, past where it will no longer fit in the package.
Parallax may even be able to offer more than one assembly option, mounting different sizes Cyclone V.
From what I understand, the Cyclone V has better routing than the IV and the LEs are more powerful. So potentially there are some gains to be had with the V family.
We would certainly opt for the -A9, but it doesn't work with free Quartus Web Edition. You'd need to buy the $3k/year licensed version to compile for that part.
This means being able to run a reasonable chunk of a P3 on the primary board. Given a successful, and potentially customizable P2, that project is likely to be very interesting!
And that means I'll figure out how to fund the Parallax board, and a significant chunk of it's value will be "center of gravity" on these efforts. Having a lot of different FPGA platforms out there will dilute and complicate things. This is undesirable, and frankly the appeal of this whole thing is either worth some personal investment, or it's not. Simple numbers aren't meaningful in the same sense as they are for chips. Some investment will qualify participants and I think we need that.
(I'll likely do some contract work on weekends to get the thing paid for, if nothing else)
Having applied that logic to the DE2, I'm pleased with the result.
Down deep, I'm kind of hoping we can get to some, "design it, test it, get it made in silicon model" because it aligns very well with the growing "maker" movement, and it aligns very well with the many complex, highly specialized, often non-accessible devices out there. I look at the spec sheets, block diagrams, dev kits, and I see a lot of convergence on the same sets of ideas with some variations bolted on here and there. It's a mess!
Better targeted and accessible silicon is a growing niche. I also believe, and have been researching, products in general, and better, well targeted products are also on the rise and a lot of the differentiation falls along the lines of user interaction and enabling / supporting hardware required. Typically, this means crude user interfaces, or the need for a PC / Tablet, etc... which complicate things, and most importantly, link it to that "octopus" Chip mentions from time to time.
BTW: Things like the onboard video, tasks (and yes that's complicated, but once sorted out, baked in, no OS octopus required), smart I/O pins, lots of DAC, counters, SERDES, etc... that makes reaching for superior user interaction viable! Right now, on Android, latency is a PITA. And in mobile, there is a big divide over how Apple does it, no garbage collection, code review, testing, power management as a primary thought in libraries, etc... and the Droid model, which is more sloppy. Each have their trade-offs, and the Apple devices typically have the best user interaction and overall design, but they are often a PITA to develop for and Apple themselves has to review and test in ways many find toxic, however good the end result is. On the Droid end of things, just about anybody can jump in, but then the cost is a less robust overall experience, and fragmentation of sorts. Also, latency. Sometimes lots of it. I'm not a fan of that aspect of Droid so far. Frankly, I've not found a low latency UX experience on Droid yet. I'm sure it's out there, and I'm sure they worked their arses off for it too...
Secondly, platforms are being shrunk down right now in an attempt to get at this smart device movement, and the problem is all the legacy baggage being carried forward, need for complex OS / kernel software, drivers, and other things all tend to dilute the value down, while fragmentation and differentiation remain tepid for the same kinds of reasons. The idea that we might have a basic platform on a chip is very compelling when weighed against these kinds of offerings, and we could use external RAM and some devices, or next to nothing but the essentials depending on product scope and the overall path to development and design would be remarkably similar, with high reuse potential. Of course, the highest reuse will depend on open code, and with the protection in the chip now, I really don't know how that will shake out. Hoping for goodness there.
What I've come to realize is there are a lot of great ideas out there. Many of them have seen the light of day too, but they never did reach a critical mass, so they remain in niche land, or simply not used much at all. That no branch, time slice, no loop control system Heater mentioned, is typical of these ideas that pack a punch, but do not relate to the largely homogenous silicon out there today.
The basic ideas in the P2 are distinctive, and one artifact of that is the ability to make something that has a superior user interaction model while performing well without requiring an operating system or other complex, or linked to "the octopus" software being involved.
Just recently, Ford announced a switch to QNX in it's vehicles, away from Windows! (The Ford I have is pre-Windows, thankfully.) If one were to extrapolate some, take a few lessons from ARM, etc... it doesn't take too much to realize a "Linux" in silicon may well develop quite a following for it's lean development model, perhaps on chip where warranted / desired, high performance and interactivity. That means platform on a chip, more than it means, make a cheap board, IMHO.
Where BOM costs are considered, think about this! Apple generates a BOM similar to it's peers. Now, don't get me wrong, they are smart and they do get that BOM cost down through smart sourcing, design, etc... This is notable, and others do it too. What is notable is the margins they can get for devices that offer both a very superior user interaction model, and some basic smarts built in. Nest labs is another example of this, with simple utility devices being made smart, and extremely high value. Nobody employing that model moves as many devices, but they capture margins worth doing, and most importantly, those margins are enough to fund further development, not races to the bottom.
It is these kinds of things that make the "can we work together and get to silicon?" effort seen here appear particularly compelling on a number of fronts well beyond having a successor to P1.
(we shall see how close to the mark some of that is in due time, won't we Ken?
re: We need a board that we can use for Propeller 1, 2 and 3
Speaking of Prop 3 , is there any chance you can release that one now because they are still adding features to Propeller 2 and it' going to be a while.
Just kidding. LOL
I was quite happy with the A7, but now there are 3,000 more reasons per year
Anybody see an ongoing problem here?
One COG has grown to ~24 000 LEs, those are some +2,000,000 gates?!. Don't get me wrong the features are amazing but "simple" cannot be used anymore to describe it. in an A7 can we fit 4 COGs, 4 threads each... not too shabby !... The P3 would be probably 4 times that... Than it may be better to choose whatever is affordable and big enough at the time the design is mature enough for our consumption...
Shhhhh! I'm making a killing on popcorn!
C.W.
You are the first commercial venture to make money with the P2!!
Several FPGA development boards has a small square board that holds the FPGA, flash memory, RAM, and voltage regulators only; and a second board that has IO connections.
I think this is a good idea. There are two good reasons to do this. The first is that the FPGA could be used for other projects or purposes. The second one is that it can be upgraded. Who knows if Altera would include Cyclone V A9 (or any other big FPGA) inside the free quartus edition in the future.
Ken, thanks for your comments, I understand and agree that Parallax needs its own board. I hope you could get a big discount for those 1,000 FPGAs. Digikey and mouser only shows the price for 1 unit. And Altera website also doesn't show any discount for multiple units. Also I have noticed in Altera's website that they don't have enough FPGAs in stock. They just show around 100 pieces maximum for just three or four models (all A7). The delivery time for more quantity than this is around the end of april.
I just hooked up and tested my DE0 without its adapter board and it is a totally workable solution for my testing purposes (until I get a DE2).
What about loading pre-compiled code to A9 (ie just loading a binary blob) - does that also need the $3k licensed version?
That could make sense, depends on the BGA reflow flows I guess.
If the package is the same, it becomes an order-tracking exercise at Assembly time.
Do Parallax have experience internally in BGA package place+soldering, or is this a contract run ?
Looking at
http://www.altera.com/devices/fpga/cyclone-v-fpgas/overview/cyv-overview.html
Altera says " 1. Color denotes vertical migration."
That suggests the 484 pin version has coverage over all die A2..A9, to 224 io lines
I'm not sure on the costs of the companion Loader-Flash, but if that is significant a paired-build of Flash+FPGA could make sense.
Long term yes, but someone who wants to use all 8 COGs of a P2, may be fine with pre-compiled files for a time.
A rough calc on A9 gives 301k/8 = 37.6k LE per COG ceiling.
With no numbers seen yet for a Cyclone V build, the exact LE usage may be lower than for Cyclone IV.
http://forums.parallax.com/showthread.php/153399-New-Altera-FPGA-board-perfect-for-2-3-cog-P2-emulation!-199
with 77k LE's it should fit 2-3 cogs easily, and it has enough I/O on board that it would not need an expansion module (24bpp VGA, uSD, etc)
Even at the full $200 price it will be half the cost of the really nice 150k LE parallax board, and let a lot more people in on the fun with p2/p3
While I hope the DE0-Nano will still be supported (missing some features) I think we need another "lower end" emulation platform, and $150-$200 for the De1-SoC is an excellent low/mid range choice.
Yes, ideally, a choice of target builds will be available, for the other Cyclone V price point boards out there.
We still do not know if the very affordable BeMicro will fit a COG, as there are no Cyclone V build stats I've seen yet.
Altera do show 2 parts (25k & 49k) in the smallest package vertical migration, so that means a larger "BeMicro Plus" may just be a build decision away.
I have a DE0 that has been without a breakout board since I bought it in July, so I've been without video since then. Puts quite a damper on my fun. But I am anxiously anticipating the Parallax Cyclone V board and will be purchasing one as soon as they are available, so considering the crazy cost of such a small run I can't see how it makes sense to do it. Even more important is to not spend the time on such a thing. But if anyone has an old, unused DE0 board they can part with, I'd certainly appreciate it!
No. That could be done for free, but it would exclude forum members from being able to compile the Verilog themselves and try out new ideas of their own.
Bart,
Check out post#51 above. Have I got a deal for you!!