I need help with asm code pls
Rick_H
Posts: 116
I am trying to write a generic asm I2C script for my project and am having a problem with isolating a bit in an integer. <-- I think that's the problem.
hear is my code for the buss
its hardly finished I am just trying to output the address to get started and then I will loop through all the channels and data that will be in outputs. its an 8 channel 8 bit DAC.
hear is my code for the buss
con
_clkmode = xtal1 + pll16x
_xinfreq = 5_000_000
VAR
long flag, amp[8], clock
long cog
PUB start : okay
okay := cog := cognew(@entry, @flag) + 1
DAT
org ' Sets the origin at zero for this point
entry or DIRA, i2cSDA ' Sets relevant pin to an output
xor DIRA, i2cSDL ' Sets relevant pin to an output
mov time, CNT ' Current clock loaded into time
add time, off_time '
loop mov OutHolder,address 'move data to placeholder
shl OutHolder,idxL 'shift indexed bit to msb clears all higher bits
shr OutHolder,shiftR 'shift bit to lsb clears all lower bits
clkloop waitcnt time, off_time ' clock time
xor OUTA, i2cSDA 'toggle clock
xor CkState, #1 'set clock pin state indicator
waitcnt time, off_time 'wait 1/2 clock pulse
cmp CkState, #1 wz, wc 'check for low clock pulse and alow data pin change on low
if_z jmp #clkloop 'if not = 0 then finish clock pulse
cmp OutHolder,DtState 'check data pin state to data bit
if_z sub idx, #1 'if the same incrament idx
add idxL, #1 'incrament shift index for bit placement
if_z jmp #loop 'if data the same state as pin go to clock
pinSDL xor OUTA, i2cSDL ' toggle data pin
xor DtState, #1 ' toggle data state var
djnz idx, #loop ' repeate for each bit in a byte
mov idx, #8 '
mov idxL, #23
jmp #loop
Out1 long
Out2 long
Out3 long
Out4 long
Out5 long
Out6 long
Out7 long
Out8 long
OutHolder long
address long %0111_1111 ' %0101_0000
ch1 long 0
ch2 long %0000_0001
ch3 long %0000_0010
ch4 long %0000_0011
ch5 long %0000_0100
ch6 long %0000_0101
ch7 long %0000_0110
ch8 long %0000_0111
i2cSDA long %0000_1000 '3
i2cSDL long %0001_0000 '4
CkState long 0
DtState long 0
clkTime long 80000
off_time long 40000
idx long 8
idxL long 24
shiftR long 32
time res 1
t1 res 1
its hardly finished I am just trying to output the address to get started and then I will loop through all the channels and data that will be in outputs. its an 8 channel 8 bit DAC.
Comments
heres an example of how I did it. Data starts as the i2c data byte to output, shift left for each bit to output. Test the 9th bit and set the carry flag and use the muxnc instruction to output the carry flag. The whole thing is then loops the right number of times, setting and resetting SCL correctly. I assume a pull up but you can use muxnc with outa instead
shl data, #1 ' Shift left one bit test data, #$100 wc ' Check MSB muxnc dira, sdamask ' Set SDA HIGH if not zeroThe clock can be as high as 5 MHz or so, but the devices are limited to 1 MHz (IIRC) the fastest. Most devices operate in the 100 to 400 kHz region.
I am still having trouble getting this to work
hear is my updated code, I really thought this would work but the SDA pin is staying high.
con _clkmode = xtal1 + pll16x _xinfreq = 5_000_000 VAR long flag, amp[8], clock long cog PUB start : okay okay := cog := cognew(@entry, @flag) + 1 DAT org ' Sets the origin at zero for this point entry or DIRA, i2cSDA ' Sets relevant pin to an output xor DIRA, i2cSDL ' Sets relevant pin to an output mov time, CNT ' Current clock loaded into time add time, off_time ' AddressB mov OutHolder,address 'move data to placeholder loop shl OutHolder,#1 'shift indexed bit to 9th bit clkloop waitcnt time, off_time ' clock time xor OUTA, i2cSDL 'toggle clock xor CkState, #1 'set clock pin state indicator waitcnt time, off_time 'wait 1/2 clock pulse cmp CkState, #1 wz 'check for low clock pulse and alow data pin change on low if_z jmp #clkloop 'if not = 0 then finish clock pulse test OutHolder,#%1_000_0000 wc 'check data pin state to data bit pinSDL muxnc OUTA, i2cSDA ' toggle data pin djnz idx, #loop ' repeate for each bit in a byte mov idx, #8 ' reset idx jmp #AddressB 'resend address Out1 long Out2 long Out3 long Out4 long Out5 long Out6 long Out7 long Out8 long OutHolder long address long %0101_0000 ' %0101_0000 ch1 long 0 ch2 long %0000_0001 ch3 long %0000_0010 ch4 long %0000_0011 ch5 long %0000_0100 ch6 long %0000_0101 ch7 long %0000_0110 ch8 long %0000_0111 i2cSDA long %0000_1000 '3 i2cSDL long %0001_0000 '4 CkState long 0 DtState long 0 clkTime long 80000 off_time long 40000 idx long 8 idxL long 24 shiftR long 32 time res 1 t1 res 1if I just pulse the data line with no if or muxnc its a perfect on off signal but I cant seem to parse the holder data as my output.
con _clkmode = xtal1 + pll16x _xinfreq = 5_000_000 VAR long flag, amp[8], clock long cog PUB start : okay okay := cog := cognew(@entry, @flag) + 1 DAT org ' Sets the origin at zero for this point entry 'or DIRA, i2cSDA ' Sets relevant pin to an output xor DIRA, i2cSDL ' Sets relevant pin to an output mov time, CNT ' Current clock loaded into time add time, off_time ' AddressB mov OutHolder,address 'move data to placeholder loop shl OutHolder,#1 'shift indexed bit to 9th bit clkloop waitcnt time, off_time ' clock time xor OUTA, i2cSDL 'toggle clock xor CkState, #1 'set clock pin state indicator waitcnt time, off_time 'wait 1/2 clock pulse cmp CkState, #1 wz 'check for low clock pulse and alow data pin change on low if_z jmp #clkloop 'if not = 0 then finish clock pulse test OutHolder,#%1_000_0000 wc 'check data pin state to data bit pinSDL muxnc dira, i2cSDA ' toggle data pin djnz idx, #loop ' repeate for each bit in a byte mov idx, #8 ' reset idx jmp #AddressB 'resend address Out1 long Out2 long Out3 long Out4 long Out5 long Out6 long Out7 long Out8 long OutHolder long address long %0101_0000 ' %0101_0000 ch1 long 0 ch2 long %0000_0001 ch3 long %0000_0010 ch4 long %0000_0011 ch5 long %0000_0100 ch6 long %0000_0101 ch7 long %0000_0110 ch8 long %0000_0111 i2cSDA long %0000_1000 '3 i2cSDL long %0001_0000 '4 CkState long 0 DtState long 0 clkTime long 80000 off_time long 40000 idx long 8 idxL long 24 shiftR long 32 time res 1 t1 res 1I'm getting a 1 on pulse 1 , a 1 on pulse 2, a 0 on pulse 3, a 1 on pulse 4 and then it just stays at 0 forever.
I uncommented the first init of dira with i2cSDA and I get what I expect, 0101 but then it stays 0 forever
con _clkmode = xtal1 + pll16x _xinfreq = 5_000_000 VAR long flag, amp[8], clock long cog PUB start : okay okay := cog := cognew(@entry, @flag) + 1 DAT org ' Sets the origin at zero for this point entry or DIRA, i2cSDA ' Sets relevant pin to an output xor DIRA, i2cSDL ' Sets relevant pin to an output mov time, CNT ' Current clock loaded into time add time, off_time ' AddressB mov OutHolder,address 'move data to placeholder loop shl OutHolder,#1 'shift indexed bit to 9th bit clkloop waitcnt time, off_time ' clock time xor OUTA, i2cSDL 'toggle clock xor CkState, #1 'set clock pin state indicator waitcnt time, off_time 'wait 1/2 clock pulse cmp CkState, #1 wz 'check for low clock pulse and alow data pin change on low if_z jmp #clkloop 'if not = 0 then finish clock pulse test OutHolder,#%1_000_0000 wc 'check data pin state to data bit pinSDL muxnc dira, i2cSDA ' toggle data pin djnz idx, #loop ' repeate for each bit in a byte mov idx, #8 ' reset idx jmp #AddressB 'resend address Out1 long Out2 long Out3 long Out4 long Out5 long Out6 long Out7 long Out8 long OutHolder long address long %0101_0000 ' %0101_0000 ch1 long 0 ch2 long %0000_0001 ch3 long %0000_0010 ch4 long %0000_0011 ch5 long %0000_0100 ch6 long %0000_0101 ch7 long %0000_0110 ch8 long %0000_0111 i2cSDA long %0000_1000 '3 i2cSDL long %0001_0000 '4 CkState long 0 DtState long 0 clkTime long 80000 off_time long 40000 idx long 8 idxL long 24 shiftR long 32 time res 1 t1 res 1The problem are these definitions:
A long without a value just means "long align" but reserves no cog ram.
So all the registers Out1..address have the same cog address.
Change it to: and it will work...
(I had to use PASD to find this)
Andy
edit: the sda line
http://propeller.wikispaces.com/PASD
A long without data forces the next data to be placed at a long aligned address, that is an address which is a multiple of 4. This is useful if you need to be sure that some byte or word data starts at a long address. If this is already the case as in your code, then it does nothing.
So OutHolder and address was the same register with two different names. After some left shifts of OutHolder, address is zero, because the shift instruction shifts zeroes in.
Andy
I'm heaving a new problem now, hopefully I can get the debugger working.
Basically I have all my loops for address, channel , data with an ack bit each and a start and stop routine. Oddly enough the MSB is always 0 in any of the bytes I am shifting into.
The problem I am looking for is it all ways passes a 0 on the first bit shifted in. I am looking at the cog memory and stepping through the code and I can see the data getting updated but i'm not sure how exactly to pinpoint the problem. I can see the holder var get updated and shifted but I am kinda stuck their atm.
Any suggestions on what to look for?
o and kudos on the debugger, its way bad azz.
other than not getting a 0 in the msb the code works perfectly.
con _clkmode = xtal1 + pll16x _xinfreq = 5_000_000 VAR long flag, amp[8], clock long cog PUB start : okay flag := 0 amp[0] :=1 amp[1] :=2 amp[2] :=3 amp[3] :=4 amp[4] :=5 amp[5] :=6 amp[6] :=7 amp[7] :=8 clock := 250 waitcnt(clkfreq + cnt) dbg.start(31,30,@entry) okay := cog := cognew(@entry, @flag) + 1 repeat waitcnt(clkfreq/2000 + cnt) flag := 2 amp[0] +=1 amp[1] +=2 amp[2] +=3 amp[3] +=4 amp[4] +=5 amp[5] +=6 amp[6] +=7 amp[7] +=8 DAT org entry ' Sets the origin at zero for this point or DIRA, i2cSDA ' Sets relevant pin to an output xor DIRA, i2cSDL ' Sets relevant pin to an output xor OUTA, i2cSDL xor OUTA, i2cSDA xor CkState, #1 mov time, CNT ' Current clock loaded into time add time, off_time loadData mov t1, par rdlong asmflag, t1 test asmflag, #2 wz waitcnt time, clkTime if_z jmp #loadData add t1, #4 rdlong out1, t1 add t1, #4 rdlong out2, t1 add t1, #4 rdlong out3, t1 add t1, #4 rdlong out4, t1 add t1, #4 rdlong out5, t1 add t1, #4 rdlong out6, t1 add t1, #4 rdlong out7, t1 add t1, #4 rdlong out8, t1 add t1, #4 rdlong off_time, t1 wrlong ch1, par mov time, CNT ' Current clock loaded into time add time, off_time call #starti2c AddressB mov OutHolder,address mov t1, #0 jmp #loop ch1Add mov OutHolder,ch1 mov t1, #1 jmp #loop ch1data mov OutHolder,Out1 mov t1, #2 jmp #loop ch2Add mov OutHolder,ch2 mov t1, #3 jmp #loop ch2data mov OutHolder,Out2 mov t1, #4 jmp #loop ch3Add mov OutHolder,ch3 mov t1, #5 jmp #loop ch3data mov OutHolder,Out3 mov t1, #6 jmp #loop ch4Add mov OutHolder,ch4 mov t1, #7 jmp #loop ch4data mov OutHolder,Out4 mov t1, #8 jmp #loop ch5Add mov OutHolder,ch5 mov t1, #9 jmp #loop ch5data mov OutHolder,Out5 mov t1, #10 jmp #loop ch6Add mov OutHolder,ch6 mov t1, #11 jmp #loop ch6data mov OutHolder,Out6 mov t1, #12 jmp #loop ch7Add mov OutHolder,ch7 mov t1, #13 jmp #loop ch7data mov OutHolder,Out7 mov t1, #14 jmp #loop ch8Add mov OutHolder,ch8 mov t1, #15 jmp #loop ch8data mov OutHolder,Out8 mov t1, #16 jmp #loop loop shl OutHolder,#1 'shift indexed bit to 9th bit clkloop waitcnt time, off_time ' clock time xor OUTA, i2cSDL 'toggle clock xor CkState, #1 'set clock pin state indicator waitcnt time, off_time 'wait 1/2 clock pulse cmp CkState, #1 wz 'check for low clock pulse and alow data pin change on low if_z jmp #clkloop 'if not = 0 then finish clock pulse test OutHolder,#%1_000_0000 wc 'check data pin state to data bit pinSDA muxc OUTA, i2cSDA ' toggle data pin djnz idx, #loop ' repeate for each bit in a byte mov idx, #9 ' reset idx cmp t1, #0 wz if_z jmp #ch1Add cmp t1, #1 wz if_z jmp #ch1data cmp t1, #2 wz if_z jmp #ch2Add cmp t1, #3 wz if_z jmp #ch2data cmp t1, #4 wz if_z jmp #ch3Add cmp t1, #5 wz if_z jmp #ch3data cmp t1, #6 wz if_z jmp #ch4Add cmp t1, #7 wz if_z jmp #ch4data cmp t1, #8 wz if_z jmp #ch5Add cmp t1, #9 wz if_z jmp #ch5data cmp t1, #10 wz if_z jmp #ch6Add cmp t1, #11 wz if_z jmp #ch6data cmp t1, #12 wz if_z jmp #ch7Add cmp t1, #13 wz if_z jmp #ch7data cmp t1, #14 wz if_z jmp #ch8Add cmp t1, #15 wz if_z jmp #ch8data cmp t1, #16 wz call #stopi2c if_z jmp #loadData starti2c waitcnt time, off_time ' clock time xor OUTA, i2cSDA 'toggle clock waitcnt time, off_time ' clock time xor OUTA, i2cSDL 'toggle clock xor CkState, #1 'set clock pin state indicator waitcnt time, off_time starti2c_ret ret stopi2c waitcnt time, off_time ' xor OUTA, i2cSDL 'toggle clock xor CkState, #1 waitcnt time, off_time xor OUTA, i2cSDA 'toggle clock waitcnt time, off_time stopi2c_ret ret Out1 long %1111_1111 Out2 long %1111_1110 Out3 long %1111_1101 Out4 long %1111_1011 Out5 long %1111_0111 Out6 long %1110_1111 Out7 long %1101_1111 Out8 long %1011_1111 OutHolder long %0111_1111 address long %1101_0000 ' %0101_0000 ch1 long 0 ch2 long %0000_0001 ch3 long %0000_0010 ch4 long %0000_0011 ch5 long %0000_0100 ch6 long %0000_0101 ch7 long %0000_0110 ch8 long %0000_0111 i2cSDA long %0000_1000 '3 i2cSDL long %0001_0000 '4 CkState long 0 DtState long 0 clkTime long 8000 off_time long 400000 idx long 9 asmflag long 0 time res 1 t1 res 1You shift first the OutHolder left:
loop shl OutHolder,#1 'shift indexed bit ...and then test bit 7 so the MSB is never checkedPerhaps you intended: test OutHolder,#%1_0000_0000 wc
Andy
Edit:
You see the Carry bit in PASD left bottom in the status bar, updated after each step.