Turning on and off RTCC interrupt in a subroutine problems??????

Stolzie · 2007-08-29 04:46

Hi guys,

I have got an issue where the RTCC interrupt keeps firing in the middle of my subroutine. I have put in code to turn the interrupt off in the subroutine before I do anything and then turn it back on after I have finished. Can I actually do this? As it doesn't seem to be working. If I turn the interrupt off at the beginning of the code, it runs perfectly.

SX48 Datasheet doesn't offer much information on this.

Any tips or suggestions, the interrupt has to stay as it is used as a base timer for timeouts in other subroutines.

Cheers

Stolzie

ReadEE
;
; Read Word at EEAddr to EEDatL,EEDatH 
; ******************************************************************************

        mov    w, #%01001000;        #(RTCC_PS_OFF)        ; setup option register
        mov    !option, w
        clrb     SPI_CS
        call    @E2Delay300nS
        clrb    SPI_CLK 
        setb    SPI_CS
        _bank SPI_BANK
        mov    spim_out_dat,#$01        ; send start bit 
        call    @spia
        ;rl,rl eeadr and then clear carry rr clear carry rr
        ;this will set bit 6,7 to known state of $00XXXXX
    ;    _bank    EEPROM_BANK
    ;    rl        EEAddr
    ;    rl        EEAddr
    ;    clc
    ;    rr        EEAddr
    ;    clc
    ;    rr        EEAddr
    ;    mov        w,EEAddr
    ;    xor        w,#$80
        _bank SPI_BANK
        mov    spim_out_dat,#$80;w        ; move $00 Control byte for EWEN
        call    @spia
        mov    spim_out_dat,#$00        ; move EEDATH
        call    @spia
        mov        globtemp1,spim_in_dat
        mov    spim_out_dat,#$00        ; move EEDATL
        call    @spia
        mov        globtemp2,spim_in_dat
        clrb    SPI_CS
        setb    SPI_CS
        _bank    EEPROM_BANK
        mov        EEDatH,globTemp1
        mov        EEDatL,globTemp2
        mov    w, #(RTCC_PS_OFF)        ; setup option register
        mov    !option, w
        retp

Guenther Daubach · 2007-08-29 07:45

Stolzie,

depending on how often the interrupt is fired, and how many clock cycles are required to execute the instructions in the ISR, the interrupt "steals" away clock cycles from the main program (or any subroutine called from there). IOW, it slows down the execution speed of the main code. As long as the main code is not time-critical, this is not a problem. In your case, the code handles communications via the SPI bus which is not really a time-critical operation, as the code generates the bus clock. Therefore, I wonder why cour code does not work correctly when you allow for interrupts, as it normally should.

I made a similar experience in the past, and I found out that the ISR code - by mistake - did modify register contents that were supposed to be left un-touched. This can easily happen when you forget to select the correct bank within the ISR before accessing registers. So, in this case, the reason for the problem was not the interrupt per se, but bad code inside the ISR. When another bank is selected within the ISR, there is no need to restore the original bank because the FSR is automatically saved on entry, and restored on exit from the interrupt.

BTW: The SX48 also saves the contents of the MODE register when the ISR is entered, and restores it on return from the interrupt, where the "smaller" SXes don't have this feature. I just mention this here to make other lurkers aware of that fact when writing ISR code for the SX20/28.

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Greetings from Germany,

G

Stolzie · 2007-08-29 08:33

Thanks Gunther for the reply, I have checked the ISR and everything seems to be in order (banking to write to the correct register).

It is strange that the code does work without the interrupt and not when it is on.

The EEPROM I am trying to talk to is a 93LC46B

; ***********
; *** ISR ***
; ***********
    ORG    0    ; Page0

ISR

Timer        ; implement various SW timers

        ; lowest-common-denominator timer
        _bank    TIMER_BANK
        incsz    baseTimer    ; inc at 5us per tick with 50MHz clk
        jmp    :timerEnd
        mov    w,#56
        mov    baseTimer,w    ;base timer rolls over at 1khz
:LedTimer
        incsz    LEDTimerLSB
        jmp    :arpTimer
        _bank    FLAG3_BANK 
        setb    flags3.TURN_LED_OFF
        nop

:arpTimer    ; ARP-timer (used for ARP response timeouts)
        incsz    arpTimerLSB
        jmp    :Mode2Timer
        inc    arpTimerMSB    ; inc at 0.3355 seconds


:Mode2Timer
        _bank    FLAG3_BANK
        sb    flags3.MODE2_ENABLE
        jmp    :dhcpTimer      
        _bank    MTWO_BANK
        decsz    MTwoTimerL
        jmp    :dhcpTimer      
        decsz    MTwoTimerH
        jmp    :dhcpTimer
        _bank    FLAG3_BANK     
        setb    flags3.MODE2_SCAN
        _bank    MTWO_BANK
        mov    w,MTwoScanL
        _bank    TIMER_BANK
        mov    MTwoTimerL,w
        _bank    MTWO_BANK
        mov    w,++MTwoScanH
        _bank    TIMER_BANK
        mov    MTwoTimerH,w

:dhcpTimer      
        _bank   DHCP_BANK
        ; DHCP-timer (used for IP lease renewals)
        decsz    dhcpBaseTimer0
        jmp    :timerEnd
        decsz    dhcpBaseTimer1
        jmp    :timerEnd
        mov    w,#4
        mov    dhcpBaseTimer1,w
        mov    w,#232
        mov    dhcpBaseTimer0,w
        incsz   dhcpTimer0      ; inc at 1s per tick
        jmp     :timerEnd
        incsz   dhcpTimer1      ; inc at 256s per tick
        jmp     :timerEnd
        incsz   dhcpTimer2      ; inc at 65536s per tick
        jmp     :timerEnd
        inc     dhcpTimer3      ; inc at 16777216s per tick                

:timerEnd
        mov    w,#-250
ISRExit        retiw

Guenther Daubach · 2007-08-29 16:55

Stolzie,

in the ISR code you have posted, following the ":LedTimer" label, you do a "_bank FLAG3_BANK", set the "TURN_LED_OFF" flag, and after the "nop", you continue with "incsz arpTimerLSB", and eventually you also do an "inc arpTimerMSB".

Are those two timer registers really located in the "FLAGS3_BANK" (the active bank at that time)? If not, you would mess up some other registers here. So you better replace the "nop" with a "_bank TIMER_BANK".

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Greetings from Germany,

G

Stolzie · 2007-08-30 01:12

Thanks Gunther, obviously I missed that one! Will fix that up and try again to see what happens.

Cheers

Stolzie

PJMonty · 2007-08-30 16:43

Stolzie,

It's not clear to me why you need to turn off interrupts. You say that interrupts fire during the processing of your main routine. So what? Billions of CPUs around the world have interrupts fire off all the time. The whole point of interrupts is that they fire off, get handled, and then return control to the main loop - all without affecting the main loop.

If you've got timing sensitive issues in your main loop, then perhaps you need to think about your software architecture and move the timing critical code to the interrupt itself. One of the great things about interrupts is that they handle timing critical stuff all the time.

If you have code that just sits in a loop until a count reaches a certain value before moving on, then you've got software that blocks and grinds to a halt all the time. This type of code is hard to maintain over time as you are constantly trying to figure out how to keep things moving and stopping simultaneously.

Thank,
PeterM

Stolzie · 2007-09-03 00:35

Hi Peter,

Thanks for the reply. I have definitely got some weird stuff happening with my board/code.

I will leave the interrupts on regardless as they are needed for other pieces of code, but it seems strange that if I turn the interrupts off the same piece of code works fine and when I turn the interrupt on it doesn't!

And I am at a loss to why it is doing this weird stuff. oh well some more debugging is required!

Thanks for the reply.

Cheers

Stolzie

Stolzie · 2007-09-03 04:04

:UPDATE

I have discovered that my write code with interrupts on is functioning correctly but the read is not. It is constantly spitting back $FF, if the interrupts are disabled it will read the correct value every single time.

Cheers

Stolzie

Guenther Daubach · 2007-09-03 06:39

Stolzie,

as you had only posted part of your program, it is pretty hard to check the code for potential errors. It would be helpful to see the complete code, or at least the variable declarations.

I don't think that an active interrupt per-se causes the problem you have - there must be something inside the ISR code that messes up something outside the ISR. BTW: did you fix the missing _bank instruction in the ISR?

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Greetings from Germany,

G

Stolzie · 2007-09-03 07:17

Hi Gunther,

I fixed up the missing bank routine, and it still had the same problem. I have since tried a few things and have commented out the bank instruction that I added and the instruction below it.

;***************************
;_bank FLAG3_BANK
;setb flags3.TURN_LED_OFF
;***************************

And I am now able to read the eeprom values! Obvioulsy it may have something to do with the ISR and possibly the RETIW at the end of the interrupt.

Will post up the defines tomorrow, but at least it is starting to come together.

Cheers

Stolzie

ISR extract

; *** ISR ***
; ***********
    ORG    0    ; Page0

ISR

Timer        ; implement various SW timers

        ; lowest-common-denominator timer
        _bank    TIMER_BANK
        incsz    baseTimer    ; inc at 5us per tick with 50MHz clk
        jmp    :timerEnd
        mov    w,#56
        mov    baseTimer,w    ;base timer rolls over at 1khz
:LedTimer
        incsz    LEDTimerLSB
        jmp    :arpTimer
        ;***************************
        ;_bank    FLAG3_BANK 
        ;setb    flags3.TURN_LED_OFF
        ;***************************
        _bank    TIMER_BANK

Stolzie · 2007-09-04 01:32

Here are the defines.

; ****************************
; *** BLANK EEPROM DEFINES ***
; ****************************

MY_ETH_ADDR0    = $0    ; Boards Basic MAC address when EEPROM blank
MY_ETH_ADDR1    = $11    ;  "
MY_ETH_ADDR2    = $BA    ;  "
MY_ETH_ADDR3    = $0    ;  "
MY_ETH_ADDR4    = $0    ;  "
MY_ETH_ADDR5    = $1    ;  "


; INCLUDE "SX52.inc"
; SX52.inc

;*********************************************************************************
; SX48BD/52BD Mode addresses
; *On SX48BD/52BD, most registers addressed via mode are read and write, with the
; exception of CMP and WKPND which do an exchange with W.
;*********************************************************************************
; Timer (read) addresses
TCPL_R        =    $00    ; Read Timer Capture register low byte
TCPH_R        =    $01    ; Read Timer Capture register high byte
TR2CML_R    =    $02    ; Read Timer R2 low byte
TR2CMH_R    =    $03    ; Read Timer R2 high byte
TR1CML_R    =    $04    ; Read Timer R1 low byte
TR1CMH_R    =    $05    ; Read Timer R1 high byte
TCNTB_R        =    $06    ; Read Timer control register B
TCNTA_R        =    $07    ; Read Timer control register A

; Exchange addresses
CMPW        =    $08    ; Exchange Comparator enable/status register with W
WKPND        =    $09    ; Exchange MIWU/RB Interrupts pending with W

; Port setup (read) addresses
WKED_R        =    $0A    ; Read MIWU/RB Interrupt edge setup, 0 = falling, 1 = rising
WKEN_R        =    $0B    ; Read MIWU/RB Interrupt edge setup, 0 = enabled, 1 = disabled
ST_R        =    $0C    ; Read Port Schmitt Trigger setup, 0 = enabled, 1 = disabled
LVL_R        =    $0D    ; Read Port Level setup, 0 = CMOS, 1 = TTL
PLP_R        =    $0E    ; Read Port Pull-up setup, 0 = enabled, 1 = disabled
DIR_R        =    $0F    ; Read Port Direction

; Timer (write) addresses
TR2CML_W    =    $12    ; Write Timer R2 low byte
TR2CMH_W    =    $13    ; Write Timer R2 high byte
TR1CML_W    =    $14    ; Write Timer R1 low byte
TR1CMH_W    =    $15    ; Write Timer R1 high byte
TCNTB_W        =    $16    ; Write Timer control register B
TCNTA_W        =    $17    ; Write Timer control register A

; Port setup (write) addresses
WKED_W        =    $1A    ; Write MIWU/RB Interrupt edge setup, 0 = falling, 1 = rising
WKEN_W        =    $1B    ; Write MIWU/RB Interrupt edge setup, 0 = enabled, 1 = disabled
ST_W        =    $1C    ; Write Port Schmitt Trigger setup, 0 = enabled, 1 = disabled
LVL_W        =    $1D    ; Write Port Level setup, 0 = CMOS, 1 = TTL
PLP_W        =    $1E    ; Write Port Pull-up setup, 0 = enabled, 1 = disabled
DIR_W        =    $1F    ; Write Port Direction

;*********************************************************************************
; Setup and enable RTCC interrupt, WREG register, RTCC/WDT prescaler
;*********************************************************************************

RTCC_ON        =    %10000000    ; Enables RTCC at address $01 (RTW hi)
                    ; WREG at address $01 (RTW lo) by default
RTCC_ID        =    %01000000    ; Disables RTCC edge interrupt (RTE_IE hi)
                    ; RTCC edge interrupt (RTE_IE lo) enabled by default
RTCC_INC_EXT    =    %00100000    ; Sets RTCC increment on RTCC pin transition (RTS hi)
                    ; RTCC increment on internal instruction (RTS lo) is defalut
RTCC_FE        =    %00010000    ; Sets RTCC to increment on falling edge (RTE_ES hi)
                    ; RTCC to increment on rising edge (RTE_ES lo) is default
RTCC_PS_OFF    =    %00001000    ; Assigns prescaler to Watchdog (PSA hi)
PS_000        =    %00000000    ; RTCC = 1:2, WDT = 1:1
PS_001        =    %00000001    ; RTCC = 1:4, WDT = 1:2
PS_010        =    %00000010    ; RTCC = 1:8, WDT = 1:4
PS_011        =    %00000011    ; RTCC = 1:16, WDT = 1:8
PS_100        =    %00000100    ; RTCC = 1:32, WDT = 1:16
PS_101        =    %00000101    ; RTCC = 1:64, WDT = 1:32
PS_110        =    %00000110    ; RTCC = 1:128, WDT = 1:64
PS_111        =    %00000111    ; RTCC = 1:256, WDT = 1:128





; **************
; *** DEVICE ***
; **************


    RESET    Main
    ID    'EIO24_1'


; *****************
; *** VARIABLES ***
; *****************

; *** Global ***
GLOBAL_ORG = $0A

flags        EQU GLOBAL_ORG+0    ; various flags used by TCP/IP stack
flags2        EQU GLOBAL_ORG+1    ; various flags used by TCP/IP stack
fsrTemp        EQU GLOBAL_ORG+2    ; various flags used by TCP/IP stack ;use to be flags3 now fsrtemp
globTemp1    EQU GLOBAL_ORG+3    ; not preserved across any function
globTemp2    EQU GLOBAL_ORG+4    ; not preserved across any function
globTemp3    EQU GLOBAL_ORG+5    ; preserved across some functions

; *** Bank 0 ***
; (Don't use this bank - Difficulties with addressing Data)
    ORG    $00

; *** Bank 1 ***
    ORG    $10

NIC_BANK    = $

nicIOAddr        DS 1    ; points to currently addressed register on NIC
nicNextPktPtr        DS 1    ; points to next packet in NIC's rx queue
nicCurrPktPtr        DS 1    ; points to current packet in NIC's rx queue
nicRemoteEth0        DS 1    ; ethernet addr used for outgoing packet, overwritten by incoming packet
nicRemoteEth1        DS 1    ;  "
nicRemoteEth2        DS 1    ;  "
nicRemoteEth3        DS 1    ;  "
nicRemoteEth4        DS 1    ;  "
nicRemoteEth5        DS 1    ;  "
nicCopySrcMSB        DS 1    ; used by NICBufferCopy()
nicCopySrcLSB        DS 1    ;  "
nicCopyDestMSB        DS 1    ;  "
nicCopyDestLSB        DS 1    ;  "
nicCopyLenMSB        DS 1    ;  "
nicCopyLenLSB        DS 1    ;  "
nicCopyTemp        DS 1    ;  "

; *** Bank 2 ***
    ORG    $20
MAC_BANK    = $
TIMER_BANK    = $    ; make sure TIMER_BANK[noparse][[/noparse]7] = NIC_BANK[noparse][[/noparse]7]

baseTimer        DS 1    ; lowest/common cog in timer chain
arpTimerMSB        DS 1    ; ARP-timer count
arpTimerLSB        DS 1    ;  "
LEDTimerLSB        DS 1    ; LED-timer count
MTwoTimerL        DS 1    ; MODE2-timer count LSB
MTwoTimerH        DS 1    ; MODE2-timer count MSB


;macMyEth0        DS 1    ; My ethernet addr used for outgoing packet
macMyEth1        DS 1    ;  "
macMyEth2        DS 1    ;  "
macMyEth3        DS 1    ;  "
macMyEth4        DS 1    ;  "
macMyEth5        DS 1    ;  "


; *** Bank 3 ***
    ORG    $30

IP_BANK        = $    ; make sure IP_BANK[noparse][[/noparse]7] = NIC_BANK[noparse][[/noparse]7]

remoteIP3        DS 1    ; IP addr used for outgoing packet, overwritten by incoming packet
remoteIP2        DS 1    ;  "
remoteIP1        DS 1    ;  "
remoteIP0        DS 1    ;  "
myIP3            DS 1    ; filter value for incoming IP packets, also used in outgoing packet
myIP2            DS 1    ;  "
myIP1            DS 1    ;  "
myIP0            DS 1    ;  "
ipCheckSumMSB        DS 1    ; IP <header_checksum>
ipCheckSumLSB        DS 1    ;  "
ipLengthMSB        DS 1    ; IP <length>
ipLengthLSB        DS 1    ;  "
ipProtocol        DS 1    ; IP <protocol>
ipIdentMSB        DS 1    ; IP <identifier>, incremented each outgoing packet
ipIdentLSB        DS 1    ;  "
counter1        DS 1    ; general purpose counter variable

; *** Bank 4 ***
    ORG    $40

ARP_BANK    = $    ; make sure ARP_BANK[noparse][[/noparse]7] = NIC_BANK[noparse][[/noparse]7]

host1IP3        DS 1    ; remote host1 IP address
host1IP2        DS 1    ;  "
host1IP1        DS 1    ;  "
host1IP0        DS 1    ;  "
host1Eth0        DS 1    ; remote host1 Ethernet address
host1Eth1        DS 1    ;  "
host1Eth2        DS 1    ;  "
host1Eth3        DS 1    ;  "
host1Eth4        DS 1    ;  "
host1Eth5        DS 1    ;  "
stPktTxBufStart        DS 1    ; start address of stalled packet in NIC tx buffer





; *** Bank 5 ***
    ORG    $50

DHCP_BANK    = $

dhcpServerId3        DS 1    ; DHCP <server_identifier> = IP addr of DHCP server
dhcpServerId2        DS 1    ;  "
dhcpServerId1        DS 1    ;  "
dhcpServerId0        DS 1    ;  "
dhcpIPLeaseTm3        DS 1    ; IP lease renewal time set by the DHCP server or 1 minute if no renewal time set
dhcpIPLeaseTm2        DS 1    ;  "
dhcpIPLeaseTm1        DS 1    ;  "
dhcpIPLeaseTm0        DS 1    ;  "
dhcpBaseTimer1        DS 1    ; DHCP base timer for renewals
dhcpBaseTimer0        DS 1    ;  "
dhcpTimer3        DS 1    ; DHCP timer for renewals
dhcpTimer2        DS 1    ;  "
dhcpTimer1        DS 1    ;  "
dhcpTimer0        DS 1    ;  "
dhcpFlags        DS 1    ; flags

; dhcpFlags 
DHCP_CONFIG    = 0



; *** Bank 6 ***
    ORG    $60
UDP_BANK    = $

udpRxSrcPortMSB        DS 1
udpRxSrcPortLSB        DS 1
udpRxDestPortMSB    DS 1    ; filter value for incoming UDP packets
udpRxDestPortLSB    DS 1    ;  "
udpRxDataLenMSB        DS 1    ; length of <data> field of incoming UDP packet
udpRxDataLenLSB        DS 1    ;  "
udpTxSrcPortMSB        DS 1
udpTxSrcPortLSB        DS 1
udpTxDestPortMSB    DS 1
udpTxDestPortLSB    DS 1
udpTxDataLenMSB        DS 1    ; length of <data> field of outgoing UDP packet
udpTxDataLenLSB        DS 1    ;  "
UDPAPPSTATE        DS 1    ; Flags Register for UDP recieved Command Packet
FIFORP            DS 1    ; Read Pointer for Output Data FIFO
FIFOWP            DS 1    ; Write Pointer for Output Data FIFO
FIFOSZ            DS 1    ; Current Data Size in Output Data FIFO


; UDPAPPSTATE

CLOCKME        = UDPAPPSTATE.0
WRITEA        = UDPAPPSTATE.1
WRITEB        = UDPAPPSTATE.2
WRITEC        = UDPAPPSTATE.3
WSPEC        = UDPAPPSTATE.4
ECHOB        = UDPAPPSTATE.5
DiscoverNow    = UDPAPPSTATE.6    
RequestNow    = UDPAPPSTATE.7





; *** Bank 7 ***
    ORG    $70
EEPROM_BANK    = $
EEAddr            DS 1    ; Address 0-63
EEDatH            DS 1    ; High Byte Data
EEDatL            DS 1    ; Low Byte Data

TARGET_BANK    =    $    ;Target for Mode 2 Data

TargetEth0        DS 1    ; Target MAC Address for Mode 2 Data
TargetEth1        DS 1    ; /\
TargetEth2        DS 1    ; /\
TargetEth3        DS 1    ; /\    
TargetEth4        DS 1    ; /\
TargetEth5        DS 1    ; /\
TargetIP0        DS 1    ; Target IP Address for Mode 2 Data
TargetIP1        DS 1    ; /\
TargetIP2        DS 1    ; /\
TargetIP3        DS 1    ; /\
TargetPort0        DS 1    ; Target Port Number for Mode 2 Data
TargetPort1        DS 1    ; /\


; *** Bank 8 ***
    ORG    $80
MTWO_BANK    = $

MTwoMaskA        DS 1    ; Mode2 Mask bits for port A
MTwoMaskB        DS 1    ; Mode2 Mask bits for port B
MTwoMaskC        DS 1    ; Mode2 Mask bits for port C
MTwoScanL        DS 1    ; Mode2 Scan Rate LSB
MTwoScanH        DS 1    ; Mode2 Scan Rate MSB
MTwoFilt        DS 1    ; Mode2 Filter 
MTwoOldA        DS 1    ; Mode2 Old Value for port A
MTwoOldB        DS 1    ; Mode2 Old Value for port B
MTwoOldC        DS 1    ; Mode2 Old Value for port C
MTwoFCntA        DS 1    ; Mode2 Filter Counter for port A
MTwoFCntB        DS 1    ; Mode2 Filter Counter for port B
MTwoFCntC        DS 1    ; Mode2 Filter Counter for port C
MTwoReadA        DS 1    ; Mode2 Read Filter Value for port A
MTwoReadB        DS 1    ; Mode2 Read Filter Value for port B
MTwoReadC        DS 1    ; Mode2 Read Filter Value for port C
MTwoFlags        DS 1    ; Flags for Mode 2

; *** MTwoFlags ***

TX_PortA    = 0    ; Transmit Port A now
TX_PortB    = 1    ; Transmit Port B now
TX_PortC    = 2    ; Transmit Port C now

; *** Bank 9 ***
    ORG    $90
SPI_BANK        = $
spim_rate_counter    DS 1
spim_bit_count        DS 1
spim_in_dat            DS 1
spim_out_dat        DS 1
GPIOA_State        DS 1

ARPE_BANK        = $

hostsmIP3        DS 1    ;  host subnetmask address
hostsmIP2        DS 1    ;  "
hostsmIP1        DS 1    ;  "
hostsmIP0        DS 1    ;  "
hostgwIP3        DS 1    ;  host gateway IP address
hostgwIP2        DS 1    ;  "
hostgwIP1        DS 1    ;  "
hostgwIP0        DS 1    ;  "

;GPIO_BANK        = $



; *** Bank A ***
    ORG    $A0
FLAG3_BANK    =$

flags3        DS 1    ;used for flags

; *** flags3 ***

TURN_LED_ON        = flags3.0    ; Tell system to turn LED on
TURN_LED_OFF    = flags3.1    ; Tell system to turn LED off
MODE2_SCAN        = flags3.2    ; Flag to tell main loop to check mode 2 signals
FIFO_EEPROM        = flags3.3    ; Indicates there is data in the FIFO for the EEPROM
MODE2_ENABLE    = flags3.4    ; Tells System that Mode2 is enabled and to scan when timer expires
EEBLANK            = flags3.5    ; Tells System that EEPROM is Empty
FIXTEN            = flags3.6    ; Fix the IP at 10.10.10.10 DHCP OFF
FIX192            = flags3.7    ; Fix the IP at 192.168.0.X    DHCP OFF
    

; *** Bank B ***
    ORG    $B0
; *** Bank C ***
    ORG    $C0
;FIFO BANK 1 OF 4 used for data ring buffer for transmit data from UDP application
; *** Bank D ***
    ORG    $D0
;FIFO BANK 2 OF 4 used for data ring buffer for transmit data from UDP application
; *** Bank E ***
    ORG    $E0
;FIFO BANK 3 OF 4 used for data ring buffer for transmit data from UDP application
; *** Bank F ***
    ORG    $F0
;FIFO BANK 4 OF 4 used for data ring buffer for transmit data from UDP application



; ***************
; *** EQUATES ***
; ***************


; *** Pin Definitions ***

RA_DIR        = %00000010;%10000000
RA_OUT        = %11111111;%00000000
RA_LVL        = %11111111;%11111111
RA_PLP        = %00000000;%01111111

RB_DIR        = %11111111
RB_OUT        = %00000000
RB_LVL        = %11111111
RB_PLP        = %11111111

RC_DIR        = %11111111
RC_OUT        = %00000000
RC_LVL        = %11111111
RC_PLP        = %11111111

RD_DIR        = %11111111
RD_OUT        = %00000000
RD_LVL        = %11111111
RD_PLP        = %11111111

RE_DIR        = %11111111
RE_OUT        = %00000000
RE_LVL        = %11111111
RE_PLP        = %00000000

NIC_DATA_PORT    = re
;NIC_CTRL_PORT    = ra

;IOWB_PIN    = NIC_CTRL_PORT.5
;IORB_PIN    = NIC_CTRL_PORT.6
;IOCH_PIN    = NIC_CTRL_PORT.7

SPI_CLK  =    ra.0      ;OUTPUT
SPI_SDI    =    ra.1    ;INPUT
SPI_SDO =     ra.2    ;OUTPUT
SPI_CS =     ra.3    ;OUTPUT


; *** flags ***

RX_IS_ARP    = 0    ; incoming packet is an ARP packet
RX_IS_ICMP    = 1    ; incoming packet is an ICMP packet
RX_IS_UDP    = 2    ; incoming packet is a UDP packet
RX_IS_TCP    = 3    ; incoming packet is a TCP packet
RX_IS_IP_BCST    = 4    ; incoming packet is an IP Broadcast packet
GOT_DHCP_OFFER    = 5    ; received DHCP IP address offer
GOT_IP_ADDR    = 6    ; received an IP address assignment (recv'ed DHCP ACK)
IP_CHKSUM_LSB    = 7    ; next byte to accumulate IP checksum is LSB


; *** flags2 ***

ARP_REQ_SENT    = 0    ; indicates that an ARP request has been sent
ARP_RSP_RCVD    = 1    ; indicates that an ARP response has been received
ARP_STL_TX    = 2    ; indicates that the stalled packet is to be transmitted
GOT_RX_FRAME    = 3    ; used by NICWaitRxFrame to indicate we got one. 
GOT_IP_LEASE    = 4    ; indicates that an IP lease was granted by a DHCP server
RENEW_IP_LEASE    = 5    ; indicates an IP lease renewal is in progress
FIFO_DATA    = 6    ; Indicates there is data in the FIFO to transmit to the host
DHCP_ENABLE    = 7    ; If this is set then get IP by DHCP else use fixed IP


; available for future use

Cheers

Stolzie

Turning on and off RTCC interrupt in a subroutine problems??????

Comments