interpolating DDS

Comments

• TransistorToaster Posts: 149

  2007-04-05 02:12 edited 2007-04-05 02:12

  I'll read that. Did you ever read the AD9851 datasheeet? Do you know of any low cost DDSs?
• TransistorToaster Posts: 149

  2007-04-05 03:18 edited 2007-04-05 03:18

  Ian,
  You do know that the current propeller clock generation is based on a completely different technique?
  Tracy Allen and Pjv had a length discussion with Chip. I can't find the thread though the search function, but here are some quotes:

  Somebody said...
  
  The reason for the jitter and the birdies in the PHS mode can be understood in the time domain. The number of cycles spent HIGH and the number of cycles LOW varies from cycle to cycle for all frequencies except those that are the clock frequency divided by a power of two. For example, with frqa:=CLKFREQ/2, the output is a square wave at a frequency 1/2 the master clock, and the HIGH time = LOW time.
  010101010101010101010101.....
  If the frqa:=CLKFREQ/2-1, which is the next lower available frequency, the sequence makes up the difference by inserting an exta 0 and an extra 1 at long intervals:
  001010101010101........1101010101010101
  That adds a weak subharmonic at 2/CLKFREQ. The whole cycle consists of CLKFREQ/2-2 cycels of 01 and one cycle of 001 and one cycle of 011. The 001 cycle occurs in this sequence: phsa=0,frqa,frqa*2,... And the 011 cycle occurs in this sequence: psha=1,frqa+1,2*frqa+1,...
  
  The number and strength of the subharmonics depends on the ratio n/m in CLKFREQ*n/m. There will be fewer subharmonics for simple ratios (small denominator, m), and for a given size denominator, there are more subharmonics when the continued fraction expansion of n/m has many small convergents. I.e., the highest subharmonic content occurs when the ratio is a convergent of the golden mean, (SQR(5)+1)/2, a Fibonacci number. The sequence of 0s and 1s is sometimes referred to as a Fibonacci Rabbit Sequence, a Fractal of sorts. I know about this because I wrote a couple of papers on it having to do with coupled oscillators. Here is a reference page that even has quick time movies and a listening post:
  www.mcs.surrey.ac.uk/Personal/R.Knott/Fibonacci/fibrab.html
  
  
  Chip, you mentioned in an earlier thread that the PLL is a ring oscillator with a phase detector that locks in on "small" changes within several clock periods, or within 10 microseconds for large changes. One way to address the jitter issue would be to--optionally--stretch out the lock time to small changes by an order of magnitude. I don't know if that would be possible given the pll topology.
  
• IanM Posts: 40

  2007-04-05 04:39 edited 2007-04-05 04:39

  Yeah, I just thought Chip might be interested in the way the jitter is removed, kind of analog, but all on chip with CMOS.
  
  Not sure what you mean by "...the current propeller clock generation is based on a completely different technique". The phase/accumulator arrangement on the prop is the first half of a DDS. The high bit can be accessed directly or though the PLL. But since it's only half a DDS it generates a lot of jitter (unless division ratio is a power of 2 of the clock).
  
  It's possible to build an equivalent 20MHz DDS using 7 cogs and a look up sine table. I posted a snippet of code a while back 'cause I needed to get the code down to 7 instructions running on 7 cogs in order to have a free cog for control. But it's all theory at the moment.
  
  DDS's are great but they are so difficult to play with because of the SSOP and smaller packages. I'm hoping there'll be a version of the prop 2 in a DIP package because that's an equivalent DDS at 160MHz!
  
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  Ian Mitchell
  www.research.utas.edu.au
• TransistorToaster Posts: 149

  2007-04-05 16:41 edited 2007-04-05 16:41

  >Not sure what you mean by "...the current propeller clock generation is based on a completely different technique".
  The wording "completely" is not right. Basically, I should have said that Propeller jitter process is different from the jitter of a stand alone DDS. The whole point of the PLL that is in series after the DDS is to get rid of the jitter. Modification to the DDS will create a better reference frequency to the PLL.
• IanM Posts: 40

  2007-04-05 23:37 edited 2007-04-05 23:37

  I don't think the PLL was ever intended as a filter to the MSB of the counter as such. It does a poor job of filtering most frequencies for RF applications.
  
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  Ian Mitchell
  www.research.utas.edu.au