Duty mode output to drive Power MosFET or IGBT

Ching Lin · 2007-02-22 14:27

Hi

I am trying to use the 60Hz sine wave duty mode output to drive MosFET or IGBT. The minimum pulse width needs to be 10 uSec or higher otherwise those power devices can't catch up. How to limit the minimum pulse width to 10 or 20 uSec?

Thanks in advance.

Ching

Mike Green · 2007-02-22 15:54

Please post the code.

Phil Pilgrim (PhiPi) · 2007-02-22 17:22

Ching,

You'll probably have to dedicate a cog to a software PWM routine. The counters' DUTY mode pulse widths, at reasonable system clock frequencies, are just too short for driving MOSFETs, forcing them to spend too much time in their linear region and possibly overheating.

-Phil

Ching Lin · 2007-02-22 19:45

Mike,

Essentially I am just using Tracy Allen's "sinewave0.spin" code.
I am using DUTY single-ended for now, in real application I will need to change to DUTY differential to drive a full bridge.

CON
  _CLKMODE = XTAL1 + PLL16X
  _XINFREQ = 5_000_000
  bits     = 9
  
VAR
  long apin, afreq

PUB main
  
  apin := 0                     ' Pin0 - square, Pin1 - sine
  afreq := 3221                 ' Frequency 60 Hz
  cognew(@entry,@apin)          ' load the pasm into a cog with par pointing to apin location

DAT
        org   0   
entry   mov   ptr,par           ' ptr to paramters
        rdlong   pn,ptr         ' read in the pin to use
        add   ptr,#4            ' point to next parameter
        rdlong frqa,ptr         ' read in the frequency parameter
        or    amode,pn          ' amode is a cog consant for NCO mode, OR in the pin number
        shl   cat,pn            ' this will be the mask to set pins pn and pn+1 as outputs
        add   pn,#1             ' next pin
        or    bmode,pn          ' bmode is cog constant for duty mode, OR in the pin number
        mov   ctra,amode        ' counter A set to NCO mode tied to pin pn
        mov   frqb,center       ' this is the 50% duty for counter B in duty mode
        mov   ctrb,bmode        ' counter B set to duty mode tied to pin pn+1
        mov   dira,cat          ' set pins used to output

        mov   T,cnt
loop    add   T,dT
        waitcnt T,dT 

        mov   phx,phsa          ' main loop looks at counter A phase
        shr   phx,#19           ' shift to make it 13 bits for full circle
        call  #getsin           ' find sine of phase
        shl   phx,#15           ' it returns 16 bits signed, make it 32 bits +/- $8000_0000
        add   phx,center        ' offset to center, 0 to $ffff_ffff (actually $1_0000 to $FFFE_0000)
        mov   frqb,phx          ' update duty of counter b

        add   ptr,#4
        wrlong frqb,ptr

        jmp   #loop

getsin  test phx,sin_90 wc      'get quadrant 2|4 into c  
        test phx,sin_180 wz     'get quadrant 3|4 into nz
        negc phx,phx            'if quadrant 2|4, negate offset
        or phx,sin_table        'or in sin table address >> 1
        shl phx,#1              'shift left to get final word address
        rdword phx,phx          'read word sample from $E000 to $F000
        negnz phx,phx           'if quadrant 3|4, negate sample
getsin_ret      ret             ' (this subroutine adapted from Prop manual)

sin_90        long      $0800
sin_180       long      $1000
sin_table     long      $E000 >> 1       'sine table base shifted right, because program does *2 to convert to word addrs
center        long      $8000_0000
amode         long      %0_00100_000_00000000_000000_000_000000                 'NCO mode
bmode         long      %0_00110_000_00000000_000000_000_000000                 'Duty mode
cat           long      3
dT            long      |< bits - 1 
phx           res       1
ptr           res       1
pn            res       1
T             res       1

Thanks,
Ching

Phil,

I thought about using another cog in logic mode to extend the timing slot too, but I am new to this and unable to come up with any scheme.

Thanks,
Ching

Mike Green · 2007-02-22 21:08

Just as an incidental finding, at the end of "loop", you've got an "add ptr,#4" followed by "wrlong frqb,ptr". You're probably missing a "mov ptr,PAR".

You might try right shifting the FRQB value 9 bits before loading it into FRQB. This would slow down the duty cycle by about a factor of 500 from about 25ns to about 12us at midpoint.

Phil Pilgrim (PhiPi) · 2007-02-22 21:38

Unless my understanding of the DUTY mode and/or the app under consideration is completely off — and it might be! — I don't think there's anything you can do to widen the output pulses, short of reducing the system clock frequency. The reason is that PHSx is incremented by FRQx on each system clock, and the output pin is driven by the carry out of PHSx, which could be only one system clock cycle wide. Lowering the value of FRQx will only make the output pulses further apart; it won't widen them.

Please correct me if I've misunderstood something here, but I've always assumed that DUTY mode outputs could never be used as a substitute for PWM when driving MOSFETs due to the extremely narrow pulse widths.

Thanks,
Phil

Post Edited (Phil Pilgrim (PhiPi)) : 2/22/2007 10:01:27 PM GMT

Ching Lin · 2007-02-22 21:46

Mike,

I had the "mov ptr,PAR" at the assembly entry and I used "add ptr,#4" & "wrlong frqb,ptr" for debug only that I forgot to delete them.

The output sine wave disappear after I insert "shr phx,#9" above "mov frqb,phx". Did I miss something else?

Thanks,
Ching

Mike Green · 2007-02-22 22:22

Sorry, I don't think my idea will work. On the other hand, with 10-20us to "play around with", you could do the whole thing in regular assembly without recourse to the counters. You have two values that must add up to about 1000 or 1024. One represents the off time and one is the on time (in system clocks). The sine wave lookup is done every time through the loop and consumes about 12-15 instructions or about 600-750ns. Essentially, you have:

:loop  ' You could put the sine calculation here
        mov      temp,#1000+8    ' Total time (+ minimum)
        sub       temp,value           '  Compute the difference
        add       temp,cnt              '  Add in system counter
        waitcnt temp,#0              '  Wait for that time
        xor       outa,bitMask        '   Toggle the I/O pin
        add      value,#8              '  Adjust for minimum time
        add      value,cnt             '  Add in system counter
        waitcnt value,#0             '  Wait for that time
        xor       outa,bitMask       '  Toggle the I/O pin
        jmp      #:loop

Essentially this takes a value between 0 and 1000, sets a minimum width of about 250ns and a maximum width of about 12.75us with a repetition rate of about 25us. You can add the sine calculation for the 0-1000 value and use the extra cycles to increase the minimum on time.

Tracy Allen · 2007-02-23 03:20

Chin Lin,

Is the issue that no individual dwell time (high or low) can be less than 10 microseconds? If that is the case, Mike's scheme, like the DUTY scheme would still be too fast.

In 1/60 of a second there are only 1667 intervals of 10 microseconds.

My first thought was to use a hardware pulse stretcher with the DUTY output, to create a 10 microsecond pulse out of each 12.5ns DUTY pulse. The dead space between each DUTY pulse would have to be longer than 10 microseconds. With clkfreq=80mhz, there are 800 clocks in one 10 microsecond interval, so FRQb<5368709 would be the condition, and the sinus could modulate up to that limit. An external pulse strecher is not a very nice solution though.

The Prop should do it on its own. I'm thinking of a lookup table of output state vs phase, something like Don Lancaster's magic sine waves.

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Tracy Allen
www.emesystems.com

Phil Pilgrim (PhiPi) · 2007-02-23 06:01

I really like the magic sinewaves approach. Tracy, thanks for pointing it out! I'd never heard of it until today. What makes it nifty for the Prop is that the pulse edges can be adjusted with a 12.5ns granularity, which should result in some really clean signals. The optimization software would have to observe the minimum 10µS edge separation constraints, which might entail a custom optimizer, as I doubt the online optimizers take this into consideration. This would be a nice problem for a genetic algorithm!

-Phil

Graham Stabler · 2007-02-23 08:49

Ching,

Where is your 10us value comming from?

Graham

Ching Lin · 2007-02-23 12:50

Tracy,

No, LOW can be much less than 10uS.
The Prop output will be connected to a 600V high and low side driver. A pulse strecher is something worth considering for us.

Thanks,
Ching

Graham,

It is a high voltage application, 10us mainly comes from the consideration of power conversion efficiency.

Thanks,
Ching

Graham Stabler · 2007-02-23 13:57

So basically you dissipate energy on switching the IGBT and have to ensure the switchings are sufficiently infrequent for low power loss. So even if you did extend the pulses the effective switching frequency would not change??

Mike's approach looks like a good one, proper PWM.

Graham

Phil Pilgrim (PhiPi) · 2007-02-24 20:58

Regarding the "magic sinewaves" approach: I wonder if it's really necessary to analyze the goodness-of-fit in the frequency domain. It seems like it might be easier to model the lowpass filtering (first-order IIR, at least) in the time domain and use a sum-of-squares error function to determine fitness.

Modelling in the frequency domain does have the advantage of not having to consider the filtering until after the fact, but computing the error function for each candidate pulse stream is more computationally complex.

-Phil

Tracy Allen · 2007-02-25 04:49

Hi Phil,
I'm going to start another thread for the magic sine waves. It might be relevant for Ching's question, but it is topic in itself. I think it might be relevant because the magic sine waves (to borrow Graham's words) "ensure the switchings are sufficiently infrequent for low power loss". It appears that the magic sine waves are intended as an improvement on standard PWM techniques, primarily for driving motors in a bridge configuration.

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Tracy Allen
www.emesystems.com

Duty mode output to drive Power MosFET or IGBT

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