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Propeller Current Draw? — Parallax Forums

Propeller Current Draw?

MX21MX21 Posts: 7
edited 2006-04-16 02:35 in Propeller 1
How much power will the propeller require?· I can't find it specified anywhere.

Thanks,

MX
·

Comments

  • Paul BakerPaul Baker Posts: 6,351
    edited 2006-04-14 20:16
    Thats a loaded question (all puns intended), anywhere from 3µA to 75mA depending on clock speed and number of cogs running. This does not take into account any external loads which can be upto 50mA/pin (characterization·of all 32 pins sinking/sourcing 50mA has not been done, so don't expect the propeller to be capable of it·since thats more than 1.5 amps total current).

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    1+1=10
  • MX21MX21 Posts: 7
    edited 2006-04-14 20:55
    I'm thinking I'll be using all 8 cogs at max speed. That would be approximately 75mA then?

    MX
  • Paul BakerPaul Baker Posts: 6,351
    edited 2006-04-14 20:58
    Correct.

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    1+1=10
  • Tracy AllenTracy Allen Posts: 6,656
    edited 2006-04-15 22:59
    My tests so far, this with one single cog running. The following is based on the beta version, so please take it with a grain of salt. I've heard that the RCslow current will be less in the production silicon. All of these currents are, in general, a big wow, remarkably low.

    RCslow  (~20khz)  70 microamps 
RCfast (~12mhz)  0.8 milliamps
RCfast with xtal 5mz activated but chip still running on RCfast   1.12 milliamps
xtal (5mhz) 0.6 milliamps   pll off
xtal (5mhz) + pll1x (5mhz) 1.3 milliamps (The pll itself operates at 80mhz, x1 is a tap)
xtal (5mhz) + pll8x (40mhz)  2.9 milliamps
xtal (5mhz) + pll16x (80mhz) 4.8 milliamps

reset (reset button pressed)  0.8 milliamps
programming (being programmed F11 from PC, propeller uses 12mhz RCfast) 3.9 milliamps
brownout occurs at around 2.7 volts, at 2.5 volts 0.2 milliamp, at 2.2 volts 0.09 milliamp

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    Tracy Allen
    www.emesystems.com
  • cgraceycgracey Posts: 14,133
    edited 2006-04-16 02:35
    Tracy,

    Thanks for running these tests.

    We've got the new silicon in now, and the quiescent currents have dropped WAY down. On the silicon you tested here, the COG memories' sense amps are initially (until the COG is run) held open when they shouldn't be, causing a chip-wide draw of an extra 50-150uA. The new silicon takes only 4.5uA w/brown-out and internal oscillator running, plus 3uA per COG at the internal 20KHz rate.

    (You know about the following, but for the sake of anyone else who may be interested...)

    The reason that the running power is so low is because the Propeller has extensive clock-gating. This·is a·BIG TABOO in the usual standard-cell-based design flow·that perhaps every modern processor is built in. Standard cell flows let you make high-level changes very quickly, but then you must spend very considerable time insuring that the computer-generated layout will meet your timing requirements. This basically comes down to managing chaos and is often punctuated by sporadic needle-in-haystack searches for problems (except the haystack looks more like·a city-wide rat's nest). Not to worry, there are million-dollar software tools that can be used to help you here. The tools we used cost only·$20k (used to be $5k) from Tanner EDA.·They were completely adequate for our job, perhaps much more apt, since they are simple and unburdened.

    The Propeller was built from the inside-out, so that every functional block was actually SPICE-verified before being assembled into the chip. This took a lot more time, but made things small, fast, and lower power. It's kind of the assembly-language approach to chip design vs. the high-level compiler approach. Big companies have got ZERO patience for this kind of development. Unless it's a matter of some finite, but mission-critical block that needs this kind of attention, nothing else will get it. They'll settle for parts and pieces and whatever's available and lump the bugs. We learned from programming Windows that not much beyond a ScrollBar was trustworthy, and silicon is not that different. For the Propeller, we even made our own I/O pads. In fact, the entire chip is full-custom. Every single polygon on every layer was designed at Parallax. I don't think it's a stretch to say that this is unheard-of today.

    The way silicon technology advances, the standard cell approach just keeps getting thrown at newer technologies, so performance gains come from the newer process, not the newer (or I should say "older") design methodology. Who knows what's possible at the 45nm node via the raw approach?
    Tracy Allen said...
    My tests so far, this with one single cog running. The following is based on the beta version, so please take it with a grain of salt. I've heard that the RCslow current will be less in the production silicon. All of these currents are, in general, a big wow, remarkably low.

    RCslow  (~20khz)  70 microamps 
RCfast (~12mhz)  0.8 milliamps
RCfast with xtal 5mz activated but chip still running on RCfast   1.12 milliamps
xtal (5mhz) 0.6 milliamps   pll off
xtal (5mhz) + pll1x (5mhz) 1.3 milliamps (The pll itself operates at 80mhz, x1 is a tap)
xtal (5mhz) + pll8x (40mhz)  2.9 milliamps
xtal (5mhz) + pll16x (80mhz) 4.8 milliamps

reset (reset button pressed)  0.8 milliamps
programming (being programmed F11 from PC, propeller uses 12mhz RCfast) 3.9 milliamps
brownout occurs at around 2.7 volts, at 2.5 volts 0.2 milliamp, at 2.2 volts 0.09 milliamp

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    Chip Gracey
    Parallax, Inc.

    Post Edited (Chip Gracey) : 4/16/2006 2:39:26 AM GMT
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