Wow, I didn't realize that these 3V parts had finally come to fruition.
Someone needs to make a new HyperRAM board and try these 64MB parts. I'm focussed on SW at this time, but it'd be interesting to spin a double wide breakout board that could surface mount one or two of these parts. Didn't read the data sheet fully but am optimistic that my HyperRAM driver could probably be adapted to that reasonably easily and the faster rated speed should allow for high speed operation. Also it would be great to find a small part that could tweak the input clock phase slightly under P2 control to give finer input latency adjustments and more reliable transfers, especially at sysclk/1. The spare pins on the breakout might be possible to control such a peripheral via CLK+DATA or i2c, if these devices even exist?
Are you wanting to take this 166MHz part and put it on the other side of P2Eval pin connections? I'm thinking that at over $25 for the part in single quantities, it needs a close P2 to use as a memory controller. Connect pins 48-36 to the eval connector and put the HyperRAM on similar pins. Or, maybe Rayman can put this chip on the P2 SWaP if the pads are compatible?
Wow, I didn't realize that these 3V parts had finally come to fruition.
Someone needs to make a new HyperRAM board and try these 64MB parts. I'm focussed on SW at this time, but it'd be interesting to spin a double wide breakout board that could surface mount one or two of these parts. Didn't read the data sheet fully but am optimistic that my HyperRAM driver could probably be adapted to that reasonably easily and the faster rated speed should allow for high speed operation. Also it would be great to find a small part that could tweak the input clock phase slightly under P2 control to give finer input latency adjustments and more reliable transfers, especially at sysclk/1. The spare pins on the breakout might be possible to control such a peripheral via CLK+DATA or i2c, if these devices even exist?
Are you wanting to take this 166MHz part and put it on the other side of P2Eval pin connections? I'm thinking that at over $25 for the part in single quantities, it needs a close P2 to use as a memory controller. Connect pins 48-36 to the eval connector and put the HyperRAM on similar pins. Or, maybe Rayman can put this chip on the P2 SWaP if the pads are compatible?
Previous HyperRAM stuff I tried way back seemed to fail from around 300MHz or so and would be rather difficult to get working reliably at maximum performance for example at the higher speeds Ada uses for her emulators using with P2-EVAL and the breakout. But I believe some of that would have been P2-EVAL routing related, not necessarily the device limits themselves. However it'd still be interesting to try out these newer chips on an EVAL board to see if they could improve the situation in any way (maybe not). I imagine a dedicated closely coupled P2+HyperRAM design somewhat like the P2Stamp could benefit more from the faster chips for any applications requiring 4x higher density now.
The P2 read data sampling and clock phase is still the tricky problem to solve, since we don't have really fine control over that, just whatever is possible with async/sync clocking for clock/data pins and enabling schmitt/non-schmitt trigger inputs. @evanh has done a bunch of testing on that.
Schmitt trigger didn't help in any meaningful way. What little effect it had on phase was varied and it faded at lower frequencies than regular logic input. Flipping the registering of the data pins is the best way to shift a partial sysclock tick.
And clock registering is best reserved for adding a sysclock tick to accommodate instruction timing on the tx side when needed. It also is a partial shift on the rx too but then the data pin registration counters it naturally.
Comments
Are you wanting to take this 166MHz part and put it on the other side of P2Eval pin connections? I'm thinking that at over $25 for the part in single quantities, it needs a close P2 to use as a memory controller. Connect pins 48-36 to the eval connector and put the HyperRAM on similar pins. Or, maybe Rayman can put this chip on the P2 SWaP if the pads are compatible?
Previous HyperRAM stuff I tried way back seemed to fail from around 300MHz or so and would be rather difficult to get working reliably at maximum performance for example at the higher speeds Ada uses for her emulators using with P2-EVAL and the breakout. But I believe some of that would have been P2-EVAL routing related, not necessarily the device limits themselves. However it'd still be interesting to try out these newer chips on an EVAL board to see if they could improve the situation in any way (maybe not). I imagine a dedicated closely coupled P2+HyperRAM design somewhat like the P2Stamp could benefit more from the faster chips for any applications requiring 4x higher density now.
The P2 read data sampling and clock phase is still the tricky problem to solve, since we don't have really fine control over that, just whatever is possible with async/sync clocking for clock/data pins and enabling schmitt/non-schmitt trigger inputs. @evanh has done a bunch of testing on that.
Schmitt trigger didn't help in any meaningful way. What little effect it had on phase was varied and it faded at lower frequencies than regular logic input. Flipping the registering of the data pins is the best way to shift a partial sysclock tick.
And clock registering is best reserved for adding a sysclock tick to accommodate instruction timing on the tx side when needed. It also is a partial shift on the rx too but then the data pin registration counters it naturally.