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Prop2 pipeline overview — Parallax Forums

Prop2 pipeline overview

evanhevanh Posts: 15,192
in Propeller 2

Chip,
I want to get clarification on your pipeline diagram. Hopefully I'm clearer on how I want it clarified this time ...

        |                   |                   |                   |                   |                   |                   |
rdRAM Ib|------+            |           rdRAM Ic|------+            |           rdRAM Id|------+            |           rdRAM Ie|
        |      |            |                   |      |            |                   |      |            |                   |
latch Da|--+   +--> rdRAM Db|---------> latch Db|--+   +--> rdRAM Dc|---------> latch Dc|--+   +--> rdRAM Dd|---------> latch Dd|
latch Sa|--+   +--> rdRAM Sb|---------> latch Sb|--+   +--> rdRAM Sc|---------> latch Sc|--+   +--> rdRAM Sd|---------> latch Sd|
latch Ia|--+   +--> latch Ib|---------> latch Ib|--+   +--> latch Ic|---------> latch Ic|--+   +--> latch Id|---------> latch Id|
        |  |                |                   |  |                |                   |  |                |                   |
        |  +---------------ALU--------> wrRAM Ra|  +---------------ALU--------> wrRAM Rb|  +---------------ALU--------> wrRAM Rc|
        |                   |                   |                   |                   |                   |                   |
        |                   |stall/done = 'gox' |                   |stall/done = 'gox' |                   |stall/done = 'gox' |
        |       'get'       |      done = 'go'  |       'get'       |      done = 'go'  |       'get'       |      done = 'go'  |

Here is an old style simplified pipeline chart.

|-------------------|-------------------|-------------------|-------------------|-------------------|-------------------|
|                   |                   |      Result       |                   |                   |                   |
|    Execute (a)    |    Execute (a)    |   Writeback (a)   |                   |                   |                   |
|-------------------|-------------------|-------------------|-------------------|-------------------|-------------------|
|    Instruction    |     Operands      |                   |                   |      Result       |                   |
|     Fetch (b)     |     Fetch (b)     |    Execute (b)    |    Execute (b)    |   Writeback (b)   |                   |
|-------------------|-------------------|-------------------|-------------------|-------------------|-------------------|
|                   |                   |    Instruction    |     Operands      |                   |                   |
|                   |                   |     Fetch (c)     |     Fetch (c)     |    Execute (c)    |    Execute (c)    |
|-------------------|-------------------|-------------------|-------------------|-------------------|-------------------|
|                   |                   |                   |                   |    Instruction    |     Operands      |
|                   |                   |                   |                   |     Fetch (d)     |     Fetch (d)     |
|-------------------|-------------------|-------------------|-------------------|-------------------|-------------------|

I'd like to align this chart with your diagram. In particular, the chart does not show addressing, only data movement. It's unclear which parts of your diagram are addressing vs data movement.

Comments

  • cgraceycgracey Posts: 14,133
    edited 2023-03-30 10:52

    Evan,

    Each rdRAM operation starts a read by giving the dual-port RAM an address on the rising clock edge, or the vertical line made of "|" characters.

    On the next clock (next "|" vertical line), the data read back from the dual-port RAM is latched or used as addresses for other reads.

    The wrRAM operation starts a write by giving the dual-port RAM an address and data on the rising clock edge ("|" vertical line).

  • evanhevanh Posts: 15,192
    edited 2023-03-30 11:37

    @cgracey said:
    The wrRAM operation starts a write by giving the dual-port RAM an address and data on the rising clock edge ("|" vertical line).

    Okay, it's all about the edges. Thanks, I had been very unsure of which side of those edges both the result writeback and instruction fetch were placed. So rdRAM Ic is where the Program Counter addresses cogRAM for instruction fetch.

    Everything else falls into place now, thanks. Here's the aligned chart:

            |                   |                   |                   |                   |                   |                   |
rdRAM Ib|------+            |           rdRAM Ic|------+            |           rdRAM Id|------+            |           rdRAM Ie|
        |      |            |                   |      |            |                   |      |            |                   |
latch Da|--+   +--> rdRAM Db|---------> latch Db|--+   +--> rdRAM Dc|---------> latch Dc|--+   +--> rdRAM Dd|---------> latch Dd|
latch Sa|--+   +--> rdRAM Sb|---------> latch Sb|--+   +--> rdRAM Sc|---------> latch Sc|--+   +--> rdRAM Sd|---------> latch Sd|
latch Ia|--+   +--> latch Ib|---------> latch Ib|--+   +--> latch Ic|---------> latch Ic|--+   +--> latch Id|---------> latch Id|
        |  |                |                   |  |                |                   |  |                |                   |
        |  +---------------ALU--------> wrRAM Ra|  +---------------ALU--------> wrRAM Rb|  +---------------ALU--------> wrRAM Rc|
        |                   |                   |                   |                   |                   |                   |
        |                   |stall/done = 'gox' |                   |stall/done = 'gox' |                   |stall/done = 'gox' |
        |       'get'       |      done = 'go'  |       'get'       |      done = 'go'  |       'get'       |      done = 'go'  |


--------|-------------------|-------------------|-------------------|-------------------|-------------------|-------------------|
Operands|                   |                   |      Result       |                   |                   |                   |
Fetch(a)|    Execute (a)    |    Execute (a)    |   Writeback (a)   |                   |                   |                   |
--------|-------------------|-------------------|-------------------|-------------------|-------------------|-------------------|
        |    Instruction    |     Operands      |                   |                   |      Result       |                   |
        |     Fetch (b)     |     Fetch (b)     |    Execute (b)    |    Execute (b)    |   Writeback (b)   |                   |
--------|-------------------|-------------------|-------------------|-------------------|-------------------|-------------------|
        |                   |                   |    Instruction    |     Operands      |                   |                   |
        |                   |                   |     Fetch (c)     |     Fetch (c)     |    Execute (c)    |    Execute (c)    |
--------|-------------------|-------------------|-------------------|-------------------|-------------------|-------------------|
        |                   |                   |                   |                   |    Instruction    |     Operands      |
        |                   |                   |                   |                   |     Fetch (d)     |     Fetch (d)     |
--------|-------------------|-------------------|-------------------|-------------------|-------------------|-------------------|
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