ALTB D,S seems to ignor D += sign Extended Code Problem

Bob Drury · 2021-08-22 01:25

I am trying to understand ALTB D,S Instruction using TestB D,S . The code attached I have tried to document what I am doing. It appears to me the there is something I am doing wrong with the Offset
from D += sign extended. Help would be apreciated.
Regards and Thanks
Bob (WRD)

evanh · 2021-08-22 01:46

Ah, it's not really an offset in the normal sense. That += is a second operation that occurs after the main "alt"ering op. It updates the index for quick access to next item so that it's ready for the next iteration when looping.

evanh · 2021-08-22 01:58

That's interesting. That debug code fails to produce output from cog1 in FlexSpin.

evanh · 2021-08-22 02:11

It's like when you do say

    index := 0
loop:
    x := items[index++]
    ....
    next loop

The index starts at zero and the first item fetched is item at array position zero. The ++ incrementing is a post-increment, so item at array position one is fetched on the second pass.

evanh · 2021-08-22 03:43

Here's a FlexC version tested and working:

#include <stdint.h>
#include <stdio.h>


void  main( void )
{
    uint32_t  data[] = {0x12345678, 0x9abcdef0};
    uint32_t  base = 1<<9, index = 0, result = 0;


    _waitms( 200 );
    printf( "Before:  base = $%x   index = %d   result = $%x\n", base, index, result );

    __asm const {       // "const" prevents FCACHEing, don't need loop speed

        or  base, #data // register addressing isn't in C

        rep @.rend, #63
        altb    index, base
        testb   0-0, index  wc
        rcr result, #1
.rend
    }

    printf( " After:  base = $%x   index = %d   result = $%x\n", base, index, result );
}

Terminal output is:

Before:  base = $200   index = 0   result = $0
 After:  base = $2dc   index = 63   result = $9abcdef0

EDIT: Added "before" reporting.

evanh · 2021-08-22 04:00

Oh, actually, it is acting like a pre-increment rather than the expected post-increment ... the first bit should be bit0 of "data" but is definitely bit1 ... ya, and when removing incrementing parameter from "base" it correctly indexes bit0 of "data".

I think that's another flaw in the prop2.

EDIT: Just tested with ALTGN and it's definitely a post-increment case.

#include <stdint.h>
#include <stdio.h>


void  main( void )
{
    uint32_t  data[] = {0x12345678, 0x9abcdef0};
    uint32_t  base = 1<<9, index = 0, result = 0;


    _waitms( 200 );
    printf( "Before:  base = $%x   index = %d   result = $%x\n", base, index, result );

    __asm const {       // "const" prevents FCACHEing, don't need loop speed

        or  base, #data // register addressing isn't in C

        rep @.rend, #2
        altgn   index, base
        getnib  result
.rend
    }

    printf( " After:  base = $%x   index = %d   result = $%x\n", base, index, result );
}

Terminal output is correctly showing the data at index 1 while index is post-incremented to 2:

Before:  base = $200   index = 0   result = $0
 After:  base = $2dc   index = 2   result = $7

Bob Drury · 2021-08-22 15:35

The instruction only takes 2 clock cycles so you would think that "Alter D field of next instruction to (D[13:5] + S) & $1FF. D += sign-extended S[17:9]. (D = D +S[17.9] )" must happen during the same instruction time. Maybe the (D[13:5] + S)&$1FF occurs first then (D = D +S[17.9] ) is done by having a circuit that clocks within the instruction finnaly generating the D Field result. But there really doesn't seem to be any way to control the instruction sequencing.

Please refer to code originally sent with opening discussion at top of chat:.

Before Instruction ALTB D_ALTB,S_ALTB
'D_ALTB' = %100000 D[13:5] = 1 and 'S_ALTB' S= %10_00110001 with S[17:9] = 1 and S[8:0] = %110001 the BaseAdress =valBit0Address = %110001
this should be Offset = 1 Index =1 BaseAdress = valBit0 = %110001 which I believe should be requesting to test 'valBit2' = %110011

After Insturction ALTB D_ALTB,S_ALTB
'D_ALTB' = %100001 'S_ALTB' = %10_00110001 by testing changing bits in 'valBit1' Bit B9 the correct flag C result is found 1 for bit being 1 and 0 for bit being 0 this is using 'valBit1 = %110010
but the register should be 'valBit2' index + offset + BaseAdress . To me it looks like 'S_ALTB = %10_00110001 is not being added. It must be either this command works differently
then understood ,or not setting up parameters properly, or bug in operand. Help!!

Regards
Bob (WRD)

evanh · 2021-08-22 19:43

@"Bob Drury" said:
Please refer to code originally sent with opening discussion at top of chat:.

It was way overly complicated to read at first sitting. Another night of sleep helped ... You've got a significant bug. The "bitindex" register, as named in Chip's example code, has to be the same one in both the ALTB and TESTB instructions. The intended prefixing fails if they aren't arranged in this manner. And the prefixed D field gets overridden therefore no value in having any specific register named there either.

In your case you'd want:

                      ALTB    D_ALTB,S_ALTB
                      TESTB   0-0,D_ALTB  WC

Bob Drury · 2021-08-23 14:12

Thanks EVANH will try out
Regards
Bob

Bob Drury · 2021-08-23 18:41

Yes this works. The S[17:9] does not contain word offset like the other instructions it contains a bit offset (I thought it was a long offset). Attached program that seems to work.
Need to actually set all of the following for ALTB.thanks for help
OffsetBitIndex long 1 'To be Loaded to OffsetS[17:9]
IndexWord long 2 'To be Loaded to IndexD[13:5]
IndexBit long 9 'To be Loaded to BitIndexD[4:0]
BaseAddress long 0 'BaseAdress of Table S[8:0]
Regards
Bob (WRD)

evanh · 2021-08-24 04:14

The whole D operand, D[13:0], is one bit-index that spans the whole of cogRAM.

ALTB D,S seems to ignor D += sign Extended Code Problem

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