I'm trying to respond to a Z80 bus running at 7.3728MHz, using the WAITPEQ instruction.
Based off the apparent timing, I have less than 180ns to lower the /WAIT line, after receiving the correct match for /IORQ and Address lines.
But, I'm missing the window. See attached image.
Currently, I'm using WAITPEQ in the normal way, and then following the match with a ANDN instruction to lower the /WAIT line.
waitpeq port_base_addr,port_active_mask ' wait until we see our addresses, together with /IORQ low
andn outa,bus_wait ' set /WAIT line to active
But that is too slow, as evidenced by the traces.
What I hoped would work is to set outa to be the matching port_base_address values, and use the WR effect to change the /WAIT line as a side effect.
The /WAIT line is already set to output in the dira register, but all other pins are set to inputs.
My hope was that this would affect the outa register correctly, and allow me to hit the timing window.
or outa,port_base_addr ' configure the base address to compare with ina
' use wr effect to set /WAIT low (/INT gets hit as side effect)
waitpeq outa,port_active_mask wr ' wait until we see our addresses, together with /IORQ low
I had hoped that all 32 bits of outa would be written, and therefore hit the /WAIT as a side effect.
But, this doesn't seem to trigger the /WAIT line at all.
Is this kind of behaviour expected? Is it supported?
Would there be a better way to achieve this outcome?
Any suggestions gratefully accepted.